Unified Coverage Report :: Module

Module : prim_generic_flop

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_ndm_sync.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_ndm_sync.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_esc_timeout.u_ref_timeout.gen_nrz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_esc_timeout.u_ref_timeout.gen_nrz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_esc_timeout.u_ref_timeout.gen_nrz_hs_protocol.ack_sync.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_esc_timeout.u_ref_timeout.gen_nrz_hs_protocol.ack_sync.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_esc_timeout.u_out.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_cfg_cdc_sync0_qe.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_cdc.u_req_pwrdn_sync.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_cdc.u_req_pwrdn_sync.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_cdc.u_ack_pwrup_sync.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_cdc.u_ack_pwrup_sync.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_cdc.u_slow_cdc_sync.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_cdc.u_slow_cdc_sync.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_cdc.u_slow_ext_req_sync.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_cdc.u_slow_ext_req_sync.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_cdc.u_ip_clk_status_sync.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_cdc.u_ip_clk_status_sync.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_cdc.u_ast_sync.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_cdc.u_ast_sync.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_cdc.u_req_pwrup_sync.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_cdc.u_req_pwrup_sync.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_cdc.u_ack_pwrdn_sync.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_cdc.u_ack_pwrdn_sync.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_cdc.u_int_fsm_invalid_sync.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_cdc.u_int_fsm_invalid_sync.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_cdc.u_pwrup_chg_sync.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_cdc.u_pwrup_chg_sync.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_cdc.u_ip_clk_en_sync.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_cdc.u_ip_clk_en_sync.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_cdc.u_sleeping_sync.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_cdc.u_sleeping_sync.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_cdc.u_scdc_sync.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_cdc.u_scdc_sync.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_cdc.u_ext_req_sync.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_cdc.u_ext_req_sync.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_cdc.u_sync_flash_idle.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_cdc.u_sync_flash_idle.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_cdc.u_sync_otp.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_cdc.u_sync_otp.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_cdc.u_sync_rom_ctrl.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_cdc.u_sync_rom_ctrl.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_cdc.u_sync_rom_ctrl.gen_flops.gen_stable_chks.u_prim_flop_3rd_stage.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_cdc.u_clr_req_sync.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_cdc.u_clr_req_sync.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_slow_fsm.u_state_regs.u_state_flop.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_slow_fsm.u_main_pok_sync.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_slow_fsm.u_main_pok_sync.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_slow_fsm.u_usb_clk_en.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_prim_lc_sync_dft_en.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_prim_lc_sync_dft_en.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_prim_lc_sync_hw_debug_en.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_prim_lc_sync_hw_debug_en.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_fsm.u_state_regs.u_state_flop.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_fsm.u_fetch_en.gen_flops.u_prim_flop.u_secure_anchor_flop.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_fsm.u_slow_sync_lc_done.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_fsm.u_slow_sync_lc_done.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_fsm.u_sync_lc_done.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_fsm.u_sync_lc_done.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_fsm.u_usb_ip_clk_en.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_fsm.u_reg_otp_init.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_fsm.u_reg_lc_init.gen_generic.u_impl_generic	100.00	100.00				100.00

Module Instance : tb.dut.u_ndm_sync.u_sync_1.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_ndm_sync.u_sync_2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_esc_timeout.u_ref_timeout.gen_nrz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_esc_timeout.u_ref_timeout.gen_nrz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_esc_timeout.u_ref_timeout.gen_nrz_hs_protocol.ack_sync.u_sync_1.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_esc_timeout.u_ref_timeout.gen_nrz_hs_protocol.ack_sync.u_sync_2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_esc_timeout.u_out.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_out

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_cfg_cdc_sync0_qe.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_cfg_cdc_sync0_qe

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_cdc.u_req_pwrdn_sync.u_sync_1.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_cdc.u_req_pwrdn_sync.u_sync_2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_cdc.u_ack_pwrup_sync.u_sync_1.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_cdc.u_ack_pwrup_sync.u_sync_2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_cdc.u_slow_cdc_sync.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_cdc.u_slow_cdc_sync.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_cdc.u_slow_ext_req_sync.u_sync_1.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_cdc.u_slow_ext_req_sync.u_sync_2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_cdc.u_ip_clk_status_sync.u_sync_1.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_cdc.u_ip_clk_status_sync.u_sync_2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_cdc.u_ast_sync.u_sync_1.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_cdc.u_ast_sync.u_sync_2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_cdc.u_req_pwrup_sync.u_sync_1.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_cdc.u_req_pwrup_sync.u_sync_2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_cdc.u_ack_pwrdn_sync.u_sync_1.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_cdc.u_ack_pwrdn_sync.u_sync_2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_cdc.u_int_fsm_invalid_sync.u_sync_1.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_cdc.u_int_fsm_invalid_sync.u_sync_2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_cdc.u_pwrup_chg_sync.u_sync_1.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_cdc.u_pwrup_chg_sync.u_sync_2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_cdc.u_ip_clk_en_sync.u_sync_1.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_cdc.u_ip_clk_en_sync.u_sync_2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_cdc.u_sleeping_sync.u_sync_1.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_cdc.u_sleeping_sync.u_sync_2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_cdc.u_scdc_sync.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_cdc.u_scdc_sync.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_cdc.u_ext_req_sync.u_sync_1.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_cdc.u_ext_req_sync.u_sync_2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_cdc.u_sync_flash_idle.u_sync_1.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_cdc.u_sync_flash_idle.u_sync_2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_cdc.u_sync_otp.u_sync_1.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_cdc.u_sync_otp.u_sync_2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_cdc.u_sync_rom_ctrl.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_cdc.u_sync_rom_ctrl.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_cdc.u_sync_rom_ctrl.gen_flops.gen_stable_chks.u_prim_flop_3rd_stage.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_flops.gen_stable_chks.u_prim_flop_3rd_stage

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_cdc.u_clr_req_sync.u_sync_1.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_cdc.u_clr_req_sync.u_sync_2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_slow_fsm.u_state_regs.u_state_flop.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_state_flop

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_slow_fsm.u_main_pok_sync.u_sync_1.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_slow_fsm.u_main_pok_sync.u_sync_2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_slow_fsm.u_usb_clk_en.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_usb_clk_en

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_prim_lc_sync_dft_en.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_prim_lc_sync_dft_en.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_prim_lc_sync_hw_debug_en.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_prim_lc_sync_hw_debug_en.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_fsm.u_state_regs.u_state_flop.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_state_flop

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_fsm.u_fetch_en.gen_flops.u_prim_flop.u_secure_anchor_flop.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_secure_anchor_flop

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_fsm.u_slow_sync_lc_done.u_sync_1.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_fsm.u_slow_sync_lc_done.u_sync_2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_fsm.u_sync_lc_done.u_sync_1.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_fsm.u_sync_lc_done.u_sync_2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_fsm.u_usb_ip_clk_en.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_usb_ip_clk_en

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_fsm.u_reg_otp_init.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_reg_otp_init

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_fsm.u_reg_lc_init.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_reg_lc_init

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_generic_flop

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1
19	1	1
21	1	1

Branch Coverage for Module : prim_generic_flop

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.



	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_ndm_sync.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

Line No.	Covered	Statements
18	1	1
19	1	1
21	1	1

Branch Coverage for Instance : tb.dut.u_ndm_sync.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_ndm_sync.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

Line No.	Covered	Statements
18	1	1
19	1	1
21	1	1

Branch Coverage for Instance : tb.dut.u_ndm_sync.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_esc_timeout.u_ref_timeout.gen_nrz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

Line No.	Covered	Statements
18	1	1
19	1	1
21	1	1

Branch Coverage for Instance : tb.dut.u_esc_timeout.u_ref_timeout.gen_nrz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_esc_timeout.u_ref_timeout.gen_nrz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

Line No.	Covered	Statements
18	1	1
19	1	1
21	1	1

Branch Coverage for Instance : tb.dut.u_esc_timeout.u_ref_timeout.gen_nrz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_esc_timeout.u_ref_timeout.gen_nrz_hs_protocol.ack_sync.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

Line No.	Covered	Statements
18	1	1
19	1	1
21	1	1

Branch Coverage for Instance : tb.dut.u_esc_timeout.u_ref_timeout.gen_nrz_hs_protocol.ack_sync.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_esc_timeout.u_ref_timeout.gen_nrz_hs_protocol.ack_sync.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

Line No.	Covered	Statements
18	1	1
19	1	1
21	1	1

Branch Coverage for Instance : tb.dut.u_esc_timeout.u_ref_timeout.gen_nrz_hs_protocol.ack_sync.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_esc_timeout.u_out.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

Line No.	Covered	Statements
18	1	1
19	1	1
21	1	1

Branch Coverage for Instance : tb.dut.u_esc_timeout.u_out.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_cfg_cdc_sync0_qe.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

Line No.	Covered	Statements
18	1	1
19	1	1
21	1	1

Branch Coverage for Instance : tb.dut.u_reg.u_cfg_cdc_sync0_qe.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_cdc.u_req_pwrdn_sync.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

Line No.	Covered	Statements
18	1	1
19	1	1
21	1	1

Branch Coverage for Instance : tb.dut.u_cdc.u_req_pwrdn_sync.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_cdc.u_req_pwrdn_sync.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

Line No.	Covered	Statements
18	1	1
19	1	1
21	1	1

Branch Coverage for Instance : tb.dut.u_cdc.u_req_pwrdn_sync.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_cdc.u_ack_pwrup_sync.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

Line No.	Covered	Statements
18	1	1
19	1	1
21	1	1

Branch Coverage for Instance : tb.dut.u_cdc.u_ack_pwrup_sync.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_cdc.u_ack_pwrup_sync.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

Line No.	Covered	Statements
18	1	1
19	1	1
21	1	1

Branch Coverage for Instance : tb.dut.u_cdc.u_ack_pwrup_sync.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_cdc.u_slow_cdc_sync.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

Line No.	Covered	Statements
18	1	1
19	1	1
21	1	1

Branch Coverage for Instance : tb.dut.u_cdc.u_slow_cdc_sync.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_cdc.u_slow_cdc_sync.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

Line No.	Covered	Statements
18	1	1
19	1	1
21	1	1

Branch Coverage for Instance : tb.dut.u_cdc.u_slow_cdc_sync.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_cdc.u_slow_ext_req_sync.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

Line No.	Covered	Statements
18	1	1
19	1	1
21	1	1

Branch Coverage for Instance : tb.dut.u_cdc.u_slow_ext_req_sync.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_cdc.u_slow_ext_req_sync.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

Line No.	Covered	Statements
18	1	1
19	1	1
21	1	1

Branch Coverage for Instance : tb.dut.u_cdc.u_slow_ext_req_sync.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_cdc.u_ip_clk_status_sync.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

Line No.	Covered	Statements
18	1	1
19	1	1
21	1	1

Branch Coverage for Instance : tb.dut.u_cdc.u_ip_clk_status_sync.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_cdc.u_ip_clk_status_sync.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

Line No.	Covered	Statements
18	1	1
19	1	1
21	1	1

Branch Coverage for Instance : tb.dut.u_cdc.u_ip_clk_status_sync.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_cdc.u_ast_sync.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

Line No.	Covered	Statements
18	1	1
19	1	1
21	1	1

Branch Coverage for Instance : tb.dut.u_cdc.u_ast_sync.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_cdc.u_ast_sync.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

Line No.	Covered	Statements
18	1	1
19	1	1
21	1	1

Branch Coverage for Instance : tb.dut.u_cdc.u_ast_sync.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_cdc.u_req_pwrup_sync.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

Line No.	Covered	Statements
18	1	1
19	1	1
21	1	1

Branch Coverage for Instance : tb.dut.u_cdc.u_req_pwrup_sync.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_cdc.u_req_pwrup_sync.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

Line No.	Covered	Statements
18	1	1
19	1	1
21	1	1

Branch Coverage for Instance : tb.dut.u_cdc.u_req_pwrup_sync.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_cdc.u_ack_pwrdn_sync.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

Line No.	Covered	Statements
18	1	1
19	1	1
21	1	1

Branch Coverage for Instance : tb.dut.u_cdc.u_ack_pwrdn_sync.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_cdc.u_ack_pwrdn_sync.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

Line No.	Covered	Statements
18	1	1
19	1	1
21	1	1

Branch Coverage for Instance : tb.dut.u_cdc.u_ack_pwrdn_sync.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_cdc.u_int_fsm_invalid_sync.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

Line No.	Covered	Statements
18	1	1
19	1	1
21	1	1

Branch Coverage for Instance : tb.dut.u_cdc.u_int_fsm_invalid_sync.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_cdc.u_int_fsm_invalid_sync.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

Line No.	Covered	Statements
18	1	1
19	1	1
21	1	1

Branch Coverage for Instance : tb.dut.u_cdc.u_int_fsm_invalid_sync.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_cdc.u_pwrup_chg_sync.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

Line No.	Covered	Statements
18	1	1
19	1	1
21	1	1

Branch Coverage for Instance : tb.dut.u_cdc.u_pwrup_chg_sync.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_cdc.u_pwrup_chg_sync.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

Line No.	Covered	Statements
18	1	1
19	1	1
21	1	1

Branch Coverage for Instance : tb.dut.u_cdc.u_pwrup_chg_sync.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_cdc.u_ip_clk_en_sync.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

Line No.	Covered	Statements
18	1	1
19	1	1
21	1	1

Branch Coverage for Instance : tb.dut.u_cdc.u_ip_clk_en_sync.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_cdc.u_ip_clk_en_sync.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

Line No.	Covered	Statements
18	1	1
19	1	1
21	1	1

Branch Coverage for Instance : tb.dut.u_cdc.u_ip_clk_en_sync.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_cdc.u_sleeping_sync.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

Line No.	Covered	Statements
18	1	1
19	1	1
21	1	1

Branch Coverage for Instance : tb.dut.u_cdc.u_sleeping_sync.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_cdc.u_sleeping_sync.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

Line No.	Covered	Statements
18	1	1
19	1	1
21	1	1

Branch Coverage for Instance : tb.dut.u_cdc.u_sleeping_sync.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_cdc.u_scdc_sync.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

Line No.	Covered	Statements
18	1	1
19	1	1
21	1	1

Branch Coverage for Instance : tb.dut.u_cdc.u_scdc_sync.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_cdc.u_scdc_sync.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

Line No.	Covered	Statements
18	1	1
19	1	1
21	1	1

Branch Coverage for Instance : tb.dut.u_cdc.u_scdc_sync.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_cdc.u_ext_req_sync.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

Line No.	Covered	Statements
18	1	1
19	1	1
21	1	1

Branch Coverage for Instance : tb.dut.u_cdc.u_ext_req_sync.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_cdc.u_ext_req_sync.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

Line No.	Covered	Statements
18	1	1
19	1	1
21	1	1

Branch Coverage for Instance : tb.dut.u_cdc.u_ext_req_sync.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_cdc.u_sync_flash_idle.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

Line No.	Covered	Statements
18	1	1
19	1	1
21	1	1

Branch Coverage for Instance : tb.dut.u_cdc.u_sync_flash_idle.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_cdc.u_sync_flash_idle.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

Line No.	Covered	Statements
18	1	1
19	1	1
21	1	1

Branch Coverage for Instance : tb.dut.u_cdc.u_sync_flash_idle.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_cdc.u_sync_otp.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

Line No.	Covered	Statements
18	1	1
19	1	1
21	1	1

Branch Coverage for Instance : tb.dut.u_cdc.u_sync_otp.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_cdc.u_sync_otp.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

Line No.	Covered	Statements
18	1	1
19	1	1
21	1	1

Branch Coverage for Instance : tb.dut.u_cdc.u_sync_otp.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_cdc.u_sync_rom_ctrl.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

Line No.	Covered	Statements
18	1	1
19	1	1
21	1	1

Branch Coverage for Instance : tb.dut.u_cdc.u_sync_rom_ctrl.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_cdc.u_sync_rom_ctrl.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

Line No.	Covered	Statements
18	1	1
19	1	1
21	1	1

Branch Coverage for Instance : tb.dut.u_cdc.u_sync_rom_ctrl.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_cdc.u_sync_rom_ctrl.gen_flops.gen_stable_chks.u_prim_flop_3rd_stage.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

Line No.	Covered	Statements
18	1	1
19	1	1
21	1	1

Branch Coverage for Instance : tb.dut.u_cdc.u_sync_rom_ctrl.gen_flops.gen_stable_chks.u_prim_flop_3rd_stage.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_cdc.u_clr_req_sync.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

Line No.	Covered	Statements
18	1	1
19	1	1
21	1	1

Branch Coverage for Instance : tb.dut.u_cdc.u_clr_req_sync.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_cdc.u_clr_req_sync.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

Line No.	Covered	Statements
18	1	1
19	1	1
21	1	1

Branch Coverage for Instance : tb.dut.u_cdc.u_clr_req_sync.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_slow_fsm.u_state_regs.u_state_flop.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

Line No.	Covered	Statements
18	1	1
19	1	1
21	1	1

Branch Coverage for Instance : tb.dut.u_slow_fsm.u_state_regs.u_state_flop.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_slow_fsm.u_main_pok_sync.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

Line No.	Covered	Statements
18	1	1
19	1	1
21	1	1

Branch Coverage for Instance : tb.dut.u_slow_fsm.u_main_pok_sync.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_slow_fsm.u_main_pok_sync.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

Line No.	Covered	Statements
18	1	1
19	1	1
21	1	1

Branch Coverage for Instance : tb.dut.u_slow_fsm.u_main_pok_sync.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_slow_fsm.u_usb_clk_en.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

Line No.	Covered	Statements
18	1	1
19	1	1
21	1	1

Branch Coverage for Instance : tb.dut.u_slow_fsm.u_usb_clk_en.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_prim_lc_sync_dft_en.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

Line No.	Covered	Statements
18	1	1
19	1	1
21	1	1

Branch Coverage for Instance : tb.dut.u_prim_lc_sync_dft_en.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_prim_lc_sync_dft_en.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

Line No.	Covered	Statements
18	1	1
19	1	1
21	1	1

Branch Coverage for Instance : tb.dut.u_prim_lc_sync_dft_en.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_prim_lc_sync_hw_debug_en.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

Line No.	Covered	Statements
18	1	1
19	1	1
21	1	1

Branch Coverage for Instance : tb.dut.u_prim_lc_sync_hw_debug_en.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_prim_lc_sync_hw_debug_en.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

Line No.	Covered	Statements
18	1	1
19	1	1
21	1	1

Branch Coverage for Instance : tb.dut.u_prim_lc_sync_hw_debug_en.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_fsm.u_state_regs.u_state_flop.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

Line No.	Covered	Statements
18	1	1
19	1	1
21	1	1

Branch Coverage for Instance : tb.dut.u_fsm.u_state_regs.u_state_flop.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_fsm.u_fetch_en.gen_flops.u_prim_flop.u_secure_anchor_flop.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

Line No.	Covered	Statements
18	1	1
19	1	1
21	1	1

Branch Coverage for Instance : tb.dut.u_fsm.u_fetch_en.gen_flops.u_prim_flop.u_secure_anchor_flop.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_fsm.u_slow_sync_lc_done.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

Line No.	Covered	Statements
18	1	1
19	1	1
21	1	1

Branch Coverage for Instance : tb.dut.u_fsm.u_slow_sync_lc_done.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_fsm.u_slow_sync_lc_done.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

Line No.	Covered	Statements
18	1	1
19	1	1
21	1	1

Branch Coverage for Instance : tb.dut.u_fsm.u_slow_sync_lc_done.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_fsm.u_sync_lc_done.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

Line No.	Covered	Statements
18	1	1
19	1	1
21	1	1

Branch Coverage for Instance : tb.dut.u_fsm.u_sync_lc_done.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_fsm.u_sync_lc_done.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

Line No.	Covered	Statements
18	1	1
19	1	1
21	1	1

Branch Coverage for Instance : tb.dut.u_fsm.u_sync_lc_done.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_fsm.u_usb_ip_clk_en.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

Line No.	Covered	Statements
18	1	1
19	1	1
21	1	1

Branch Coverage for Instance : tb.dut.u_fsm.u_usb_ip_clk_en.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_fsm.u_reg_otp_init.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

Line No.	Covered	Statements
18	1	1
19	1	1
21	1	1

Branch Coverage for Instance : tb.dut.u_fsm.u_reg_otp_init.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_fsm.u_reg_lc_init.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

Line No.	Covered	Statements
18	1	1
19	1	1
21	1	1

Branch Coverage for Instance : tb.dut.u_fsm.u_reg_lc_init.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3