3df77bec1
Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
---|---|---|---|---|---|---|---|
V1 | smoke | rom_ctrl_smoke | 32.700s | 3.454ms | 47 | 50 | 94.00 |
V1 | csr_hw_reset | rom_ctrl_csr_hw_reset | 13.750s | 1.808ms | 5 | 5 | 100.00 |
V1 | csr_rw | rom_ctrl_csr_rw | 14.280s | 2.112ms | 20 | 20 | 100.00 |
V1 | csr_bit_bash | rom_ctrl_csr_bit_bash | 14.360s | 9.217ms | 5 | 5 | 100.00 |
V1 | csr_aliasing | rom_ctrl_csr_aliasing | 14.240s | 1.822ms | 5 | 5 | 100.00 |
V1 | csr_mem_rw_with_rand_reset | rom_ctrl_csr_mem_rw_with_rand_reset | 14.230s | 7.601ms | 20 | 20 | 100.00 |
V1 | regwen_csr_and_corresponding_lockable_csr | rom_ctrl_csr_rw | 14.280s | 2.112ms | 20 | 20 | 100.00 |
rom_ctrl_csr_aliasing | 14.240s | 1.822ms | 5 | 5 | 100.00 | ||
V1 | mem_walk | rom_ctrl_mem_walk | 13.060s | 2.046ms | 5 | 5 | 100.00 |
V1 | mem_partial_access | rom_ctrl_mem_partial_access | 14.810s | 8.691ms | 5 | 5 | 100.00 |
V1 | TOTAL | 112 | 115 | 97.39 | |||
V2 | max_throughput_chk | rom_ctrl_max_throughput_chk | 15.690s | 2.136ms | 50 | 50 | 100.00 |
V2 | stress_all | rom_ctrl_stress_all | 1.482m | 11.830ms | 46 | 50 | 92.00 |
V2 | kmac_err_chk | rom_ctrl_kmac_err_chk | 30.710s | 4.477ms | 50 | 50 | 100.00 |
V2 | alert_test | rom_ctrl_alert_test | 14.380s | 2.397ms | 50 | 50 | 100.00 |
V2 | tl_d_oob_addr_access | rom_ctrl_tl_errors | 16.590s | 26.746ms | 20 | 20 | 100.00 |
V2 | tl_d_illegal_access | rom_ctrl_tl_errors | 16.590s | 26.746ms | 20 | 20 | 100.00 |
V2 | tl_d_outstanding_access | rom_ctrl_csr_hw_reset | 13.750s | 1.808ms | 5 | 5 | 100.00 |
rom_ctrl_csr_rw | 14.280s | 2.112ms | 20 | 20 | 100.00 | ||
rom_ctrl_csr_aliasing | 14.240s | 1.822ms | 5 | 5 | 100.00 | ||
rom_ctrl_same_csr_outstanding | 15.050s | 17.984ms | 20 | 20 | 100.00 | ||
V2 | tl_d_partial_access | rom_ctrl_csr_hw_reset | 13.750s | 1.808ms | 5 | 5 | 100.00 |
rom_ctrl_csr_rw | 14.280s | 2.112ms | 20 | 20 | 100.00 | ||
rom_ctrl_csr_aliasing | 14.240s | 1.822ms | 5 | 5 | 100.00 | ||
rom_ctrl_same_csr_outstanding | 15.050s | 17.984ms | 20 | 20 | 100.00 | ||
V2 | TOTAL | 236 | 240 | 98.33 | |||
V2S | corrupt_sig_fatal_chk | rom_ctrl_corrupt_sig_fatal_chk | 4.801m | 146.689ms | 47 | 50 | 94.00 |
V2S | passthru_mem_tl_intg_err | rom_ctrl_passthru_mem_tl_intg_err | 4.544m | 189.222ms | 20 | 20 | 100.00 |
V2S | tl_intg_err | rom_ctrl_sec_cm | 1.674m | 1.958ms | 5 | 5 | 100.00 |
rom_ctrl_tl_intg_err | 1.200m | 7.254ms | 20 | 20 | 100.00 | ||
V2S | prim_fsm_check | rom_ctrl_sec_cm | 1.674m | 1.958ms | 5 | 5 | 100.00 |
V2S | sec_cm_checker_ctr_consistency | rom_ctrl_corrupt_sig_fatal_chk | 4.801m | 146.689ms | 47 | 50 | 94.00 |
V2S | sec_cm_checker_ctrl_flow_consistency | rom_ctrl_corrupt_sig_fatal_chk | 4.801m | 146.689ms | 47 | 50 | 94.00 |
V2S | sec_cm_checker_fsm_local_esc | rom_ctrl_corrupt_sig_fatal_chk | 4.801m | 146.689ms | 47 | 50 | 94.00 |
V2S | sec_cm_compare_ctrl_flow_consistency | rom_ctrl_corrupt_sig_fatal_chk | 4.801m | 146.689ms | 47 | 50 | 94.00 |
V2S | sec_cm_compare_ctr_consistency | rom_ctrl_corrupt_sig_fatal_chk | 4.801m | 146.689ms | 47 | 50 | 94.00 |
V2S | sec_cm_compare_ctr_redun | rom_ctrl_sec_cm | 1.674m | 1.958ms | 5 | 5 | 100.00 |
V2S | sec_cm_fsm_sparse | rom_ctrl_sec_cm | 1.674m | 1.958ms | 5 | 5 | 100.00 |
V2S | sec_cm_mem_scramble | rom_ctrl_smoke | 32.700s | 3.454ms | 47 | 50 | 94.00 |
V2S | sec_cm_mem_digest | rom_ctrl_smoke | 32.700s | 3.454ms | 47 | 50 | 94.00 |
V2S | sec_cm_intersig_mubi | rom_ctrl_smoke | 32.700s | 3.454ms | 47 | 50 | 94.00 |
V2S | sec_cm_bus_integrity | rom_ctrl_tl_intg_err | 1.200m | 7.254ms | 20 | 20 | 100.00 |
V2S | sec_cm_bus_local_esc | rom_ctrl_corrupt_sig_fatal_chk | 4.801m | 146.689ms | 47 | 50 | 94.00 |
rom_ctrl_kmac_err_chk | 30.710s | 4.477ms | 50 | 50 | 100.00 | ||
V2S | sec_cm_mux_mubi | rom_ctrl_corrupt_sig_fatal_chk | 4.801m | 146.689ms | 47 | 50 | 94.00 |
V2S | sec_cm_mux_consistency | rom_ctrl_corrupt_sig_fatal_chk | 4.801m | 146.689ms | 47 | 50 | 94.00 |
V2S | sec_cm_ctrl_redun | rom_ctrl_corrupt_sig_fatal_chk | 4.801m | 146.689ms | 47 | 50 | 94.00 |
V2S | sec_cm_ctrl_mem_integrity | rom_ctrl_passthru_mem_tl_intg_err | 4.544m | 189.222ms | 20 | 20 | 100.00 |
V2S | sec_cm_tlul_fifo_ctr_redun | rom_ctrl_sec_cm | 1.674m | 1.958ms | 5 | 5 | 100.00 |
V2S | TOTAL | 92 | 95 | 96.84 | |||
V3 | stress_all_with_rand_reset | rom_ctrl_stress_all_with_rand_reset | 2.807h | 62.754ms | 31 | 50 | 62.00 |
V3 | TOTAL | 31 | 50 | 62.00 | |||
TOTAL | 471 | 500 | 94.20 |
Items | Total | Written | Passing | Progress |
---|---|---|---|---|
V1 | 8 | 8 | 7 | 87.50 |
V2 | 6 | 6 | 5 | 83.33 |
V2S | 4 | 4 | 3 | 75.00 |
V3 | 1 | 1 | 0 | 0.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
---|---|---|---|---|---|---|---|
95.83 | 97.16 | 93.12 | 97.88 | 86.67 | 98.68 | 98.19 | 99.07 |
Job rom_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out
has 15 failures:
1.rom_ctrl_stress_all_with_rand_reset.1660794948
Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log
Job ID: smart:3db77aeb-ae89-4ba1-8612-ddb011fabafc
4.rom_ctrl_stress_all_with_rand_reset.2118501346
Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/4.rom_ctrl_stress_all_with_rand_reset/latest/run.log
Job ID: smart:4542e1c0-b449-4b71-b846-ad59a78ecc76
... and 13 more failures.
UVM_FATAL (cip_base_vseq.sv:245) [rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=*
has 10 failures:
8.rom_ctrl_stress_all.1989711918
Line 219, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/8.rom_ctrl_stress_all/latest/run.log
UVM_FATAL @ 10011531733 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x4b9bd2e7
UVM_INFO @ 10011531733 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
9.rom_ctrl_stress_all.3940152214
Line 219, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/9.rom_ctrl_stress_all/latest/run.log
UVM_FATAL @ 10009486327 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0xda85d7b3
UVM_INFO @ 10009486327 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
11.rom_ctrl_smoke.3109694212
Line 218, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/11.rom_ctrl_smoke/latest/run.log
UVM_FATAL @ 10020066403 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0xa7f87b00
UVM_INFO @ 10020066403 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
33.rom_ctrl_smoke.2104169380
Line 218, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/33.rom_ctrl_smoke/latest/run.log
UVM_FATAL @ 10005045317 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0xaecf6785
UVM_INFO @ 10005045317 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
12.rom_ctrl_stress_all_with_rand_reset.1915712541
Line 239, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/12.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 11926925874 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x89669dfc
UVM_INFO @ 11926925874 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
20.rom_ctrl_stress_all_with_rand_reset.1637619576
Line 232, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/20.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 14281697066 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x6cd727f6
UVM_INFO @ 14281697066 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
has 2 failures:
19.rom_ctrl_corrupt_sig_fatal_chk.591977697
Line 243, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/19.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
37.rom_ctrl_corrupt_sig_fatal_chk.2771491213
Line 255, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/37.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rom_ctrl_scoreboard.sv:253) [scoreboard] Check failed pwrmgr_complete == *'b* (* [*] vs * [*]) pwrmgr signals never checked
has 1 failures:
2.rom_ctrl_stress_all_with_rand_reset.1849525247
Line 320, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/2.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 126570759385 ps: (rom_ctrl_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
UVM_INFO @ 126570759385 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:595) virtual_sequencer [rom_ctrl_corrupt_sig_fatal_chk_vseq] expect alert:fatal to fire
has 1 failures:
40.rom_ctrl_corrupt_sig_fatal_chk.1511784227
Line 227, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/40.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log
UVM_ERROR @ 1996283791 ps: (cip_base_vseq.sv:595) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] expect alert:fatal to fire
UVM_INFO @ 1996283791 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---