Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_rom_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_rom_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_rom_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_rom_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_rom_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	215208	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

2194396

1

T22

35

T23

332

T24

439

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	598679	1			T22	4		T23	50		T24	115
values[0x0]	838121	1			T22	16		T23	179		T24	179
values[0x1]	972804	1			T22	20		T23	170		T24	189

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	94566	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2315038

1

T22

35

T23

348

T24

465

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	9220	1			T22	1		T25	3		T30	2
valid_sources[0x01]	9946	1			T23	3		T24	2		T28	2
valid_sources[0x02]	9986	1			T23	3		T25	2		T73	1
valid_sources[0x03]	8108	1			T23	2		T24	3		T28	1
valid_sources[0x04]	8590	1			T23	2		T44	1		T74	5
valid_sources[0x05]	9636	1			T23	2		T24	4		T25	12
valid_sources[0x06]	9028	1			T23	2		T24	9		T44	3
valid_sources[0x07]	10233	1			T28	2		T29	4		T30	1
valid_sources[0x08]	9032	1			T23	1		T25	3		T46	28
valid_sources[0x09]	8850	1			T23	2		T24	11		T25	2
valid_sources[0x0a]	8824	1			T22	1		T23	2		T24	36
valid_sources[0x0b]	9303	1			T23	1		T25	2		T44	3
valid_sources[0x0c]	9089	1			T23	6		T24	1		T64	4
valid_sources[0x0d]	9576	1			T23	1		T25	2		T64	3
valid_sources[0x0e]	8867	1			T23	2		T24	14		T28	1
valid_sources[0x0f]	9706	1			T23	5		T64	2		T44	1
valid_sources[0x10]	10533	1			T23	4		T24	4		T46	26
valid_sources[0x11]	8313	1			T23	6		T24	1		T25	2
valid_sources[0x12]	9959	1			T23	3		T30	1		T64	1
valid_sources[0x13]	8967	1			T23	3		T30	1		T46	10
valid_sources[0x14]	9648	1			T64	1		T44	1		T67	8
valid_sources[0x15]	8704	1			T23	1		T68	1		T75	9
valid_sources[0x16]	10130	1			T23	1		T66	4		T74	4
valid_sources[0x17]	9231	1			T28	3		T64	2		T44	3
valid_sources[0x18]	9420	1			T23	1		T30	1		T64	2
valid_sources[0x19]	8833	1			T23	1		T25	10		T64	3
valid_sources[0x1a]	8943	1			T23	2		T25	1		T30	1
valid_sources[0x1b]	9280	1			T23	4		T30	1		T64	2
valid_sources[0x1c]	9099	1			T23	3		T64	1		T44	3
valid_sources[0x1d]	8929	1			T22	1		T23	1		T30	3
valid_sources[0x1e]	8276	1			T23	2		T67	2		T69	1
valid_sources[0x1f]	9381	1			T44	1		T66	3		T67	7
valid_sources[0x20]	9222	1			T23	3		T24	4		T28	1
valid_sources[0x21]	9517	1			T23	2		T24	4		T25	1
valid_sources[0x22]	9180	1			T23	2		T25	3		T28	1
valid_sources[0x23]	10904	1			T24	4		T28	2		T29	8
valid_sources[0x24]	8881	1			T24	7		T28	1		T64	4
valid_sources[0x25]	8541	1			T23	2		T25	4		T26	10
valid_sources[0x26]	8239	1			T22	1		T23	1		T28	1
valid_sources[0x27]	10258	1			T23	2		T25	5		T64	1
valid_sources[0x28]	8135	1			T23	1		T28	2		T44	2
valid_sources[0x29]	8628	1			T23	1		T28	1		T30	1
valid_sources[0x2a]	9690	1			T28	3		T29	11		T30	2
valid_sources[0x2b]	9046	1			T23	1		T25	1		T29	18
valid_sources[0x2c]	9367	1			T22	2		T23	1		T25	8
valid_sources[0x2d]	9816	1			T23	4		T64	3		T44	1
valid_sources[0x2e]	9920	1			T23	4		T24	2		T30	1
valid_sources[0x2f]	9399	1			T23	1		T64	1		T44	2
valid_sources[0x30]	8400	1			T22	1		T44	6		T66	3
valid_sources[0x31]	9835	1			T27	20		T28	1		T29	5
valid_sources[0x32]	9748	1			T22	1		T28	1		T30	1
valid_sources[0x33]	9437	1			T23	3		T28	1		T44	2
valid_sources[0x34]	10470	1			T23	1		T29	10		T30	1
valid_sources[0x35]	11444	1			T25	3		T28	1		T64	1
valid_sources[0x36]	9001	1			T23	2		T24	5		T64	1
valid_sources[0x37]	9170	1			T22	1		T23	1		T25	5
valid_sources[0x38]	9304	1			T23	2		T25	3		T44	1
valid_sources[0x39]	8937	1			T22	1		T23	1		T30	2
valid_sources[0x3a]	9353	1			T23	3		T28	2		T44	2
valid_sources[0x3b]	9097	1			T22	3		T23	1		T30	1
valid_sources[0x3c]	9608	1			T23	1		T44	1		T75	5
valid_sources[0x3d]	8525	1			T25	3		T64	1		T44	4
valid_sources[0x3e]	9819	1			T22	1		T23	1		T28	1
valid_sources[0x3f]	8563	1			T22	1		T23	1		T25	1
valid_sources[0x40]	8590	1			T23	1		T27	39		T30	3
valid_sources[0x41]	9772	1			T23	2		T25	2		T30	1
valid_sources[0x42]	9707	1			T25	6		T28	1		T44	1
valid_sources[0x43]	8966	1			T23	1		T64	2		T69	1
valid_sources[0x44]	9024	1			T24	3		T25	1		T28	1
valid_sources[0x45]	10592	1			T23	4		T25	5		T28	2
valid_sources[0x46]	10714	1			T23	2		T24	4		T25	2
valid_sources[0x47]	9920	1			T23	1		T64	2		T44	3
valid_sources[0x48]	9184	1			T23	3		T25	6		T64	2
valid_sources[0x49]	9684	1			T30	1		T64	4		T44	1
valid_sources[0x4a]	10028	1			T24	1		T28	1		T64	1
valid_sources[0x4b]	8948	1			T23	2		T25	1		T44	3
valid_sources[0x4c]	9817	1			T23	1		T25	1		T65	6
valid_sources[0x4d]	10111	1			T23	1		T64	2		T44	5
valid_sources[0x4e]	9257	1			T22	1		T25	1		T30	2
valid_sources[0x4f]	9551	1			T22	1		T23	2		T24	11
valid_sources[0x50]	9564	1			T23	2		T25	2		T64	2
valid_sources[0x51]	9568	1			T23	1		T25	5		T64	2
valid_sources[0x52]	8205	1			T25	1		T64	3		T67	2
valid_sources[0x53]	9134	1			T23	1		T29	2		T44	2
valid_sources[0x54]	8936	1			T23	2		T25	12		T64	2
valid_sources[0x55]	9527	1			T23	3		T30	1		T64	1
valid_sources[0x56]	8591	1			T25	8		T46	11		T64	1
valid_sources[0x57]	9592	1			T23	2		T24	5		T25	3
valid_sources[0x58]	9863	1			T23	2		T25	2		T28	1
valid_sources[0x59]	10082	1			T23	1		T29	2		T64	2
valid_sources[0x5a]	8800	1			T22	1		T23	1		T25	9
valid_sources[0x5b]	8879	1			T30	1		T64	1		T66	13
valid_sources[0x5c]	9247	1			T23	4		T28	2		T64	1
valid_sources[0x5d]	8008	1			T25	1		T28	1		T64	3
valid_sources[0x5e]	9776	1			T25	1		T28	1		T44	2
valid_sources[0x5f]	9924	1			T25	1		T30	1		T64	1
valid_sources[0x60]	9882	1			T23	1		T24	5		T30	1
valid_sources[0x61]	8942	1			T23	2		T65	20		T73	1
valid_sources[0x62]	8042	1			T23	1		T64	3		T44	2
valid_sources[0x63]	9532	1			T23	4		T28	1		T64	5
valid_sources[0x64]	9320	1			T23	2		T24	6		T25	2
valid_sources[0x65]	9675	1			T23	2		T64	1		T44	1
valid_sources[0x66]	10208	1			T23	2		T29	2		T64	2
valid_sources[0x67]	9622	1			T23	5		T25	2		T28	3
valid_sources[0x68]	9298	1			T23	1		T25	2		T64	2
valid_sources[0x69]	9068	1			T23	2		T28	1		T30	1
valid_sources[0x6a]	9332	1			T24	1		T30	1		T64	2
valid_sources[0x6b]	9510	1			T23	2		T64	1		T44	1
valid_sources[0x6c]	8780	1			T23	5		T28	1		T30	1
valid_sources[0x6d]	9243	1			T64	4		T44	2		T65	1
valid_sources[0x6e]	9510	1			T22	2		T23	2		T25	10
valid_sources[0x6f]	9463	1			T23	5		T28	3		T44	2
valid_sources[0x70]	8776	1			T25	7		T64	1		T44	1
valid_sources[0x71]	9756	1			T23	6		T24	25		T28	2
valid_sources[0x72]	9645	1			T25	1		T29	2		T64	1
valid_sources[0x73]	10248	1			T69	3		T105	4		T84	1
valid_sources[0x74]	10338	1			T23	2		T28	2		T44	4
valid_sources[0x75]	8662	1			T22	1		T23	1		T64	2
valid_sources[0x76]	9511	1			T22	1		T23	1		T25	1
valid_sources[0x77]	8939	1			T24	22		T29	8		T44	1
valid_sources[0x78]	8798	1			T23	1		T28	2		T64	2
valid_sources[0x79]	9852	1			T23	2		T28	1		T64	3
valid_sources[0x7a]	9105	1			T64	1		T44	2		T73	1
valid_sources[0x7b]	8910	1			T22	1		T64	1		T44	2
valid_sources[0x7c]	9668	1			T24	8		T25	2		T30	1
valid_sources[0x7d]	8394	1			T23	3		T24	18		T65	11
valid_sources[0x7e]	10540	1			T23	1		T65	1		T68	1
valid_sources[0x7f]	9607	1			T24	3		T46	11		T44	1
valid_sources[0x80]	9466	1			T24	26		T27	3		T64	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

553676

1

T22

1

T23

6

T24

108

values[0x0]

all_enables

biggest_size

821340

1

T22

15

T23

167

T24

174

values[0x1]

all_enables

biggest_size

819380

1

T22

19

T23

159

T24

157

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	498509	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

2192501

1

T23

40

T24

515

T25

386

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	597729	1			T23	40		T24	111		T25	86
values[0x0]	863338	1			T24	215		T25	153		T27	218
values[0x1]	1229943	1			T24	253		T25	340		T27	245

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	188929	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2502081

1

T23

40

T24

557

T25

508

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	9870	1			T25	2		T27	14		T65	4
valid_sources[0x01]	12147	1			T24	4		T25	1		T27	9
valid_sources[0x02]	10317	1			T24	3		T25	3		T27	4
valid_sources[0x03]	9867	1			T24	20		T25	3		T69	5
valid_sources[0x04]	9749	1			T25	7		T69	2		T71	4
valid_sources[0x05]	12234	1			T25	3		T27	1		T64	5
valid_sources[0x06]	9196	1			T23	1		T25	2		T27	1
valid_sources[0x07]	10216	1			T23	1		T25	4		T27	9
valid_sources[0x08]	10191	1			T23	1		T24	2		T25	5
valid_sources[0x09]	11894	1			T25	1		T44	1		T65	1
valid_sources[0x0a]	9893	1			T25	1		T27	1		T28	2
valid_sources[0x0b]	10885	1			T24	3		T25	2		T27	7
valid_sources[0x0c]	9328	1			T24	5		T25	1		T27	1
valid_sources[0x0d]	9646	1			T24	1		T25	3		T27	2
valid_sources[0x0e]	10175	1			T25	2		T65	5		T69	3
valid_sources[0x0f]	10796	1			T25	1		T27	4		T69	2
valid_sources[0x10]	10034	1			T25	2		T27	3		T64	3
valid_sources[0x11]	11752	1			T25	3		T69	2		T76	7
valid_sources[0x12]	10746	1			T24	1		T25	5		T27	2
valid_sources[0x13]	11344	1			T23	1		T24	7		T25	1
valid_sources[0x14]	9841	1			T24	2		T25	4		T27	3
valid_sources[0x15]	11946	1			T24	4		T25	2		T65	2
valid_sources[0x16]	10459	1			T24	1		T25	3		T27	3
valid_sources[0x17]	12205	1			T25	6		T27	2		T69	2
valid_sources[0x18]	11970	1			T24	1		T25	3		T69	2
valid_sources[0x19]	11013	1			T24	7		T25	3		T67	1
valid_sources[0x1a]	10213	1			T24	2		T25	1		T27	26
valid_sources[0x1b]	9750	1			T23	1		T24	3		T25	2
valid_sources[0x1c]	9332	1			T24	4		T25	4		T27	3
valid_sources[0x1d]	9627	1			T24	5		T25	2		T27	1
valid_sources[0x1e]	9689	1			T25	2		T27	1		T64	2
valid_sources[0x1f]	11681	1			T25	2		T27	3		T64	3
valid_sources[0x20]	11725	1			T24	1		T25	2		T69	2
valid_sources[0x21]	9157	1			T25	4		T27	7		T69	3
valid_sources[0x22]	10118	1			T24	1		T27	1		T64	10
valid_sources[0x23]	9004	1			T25	2		T64	1		T69	2
valid_sources[0x24]	9832	1			T24	4		T25	1		T28	1
valid_sources[0x25]	11295	1			T24	3		T25	2		T69	4
valid_sources[0x26]	10942	1			T24	4		T25	1		T27	3
valid_sources[0x27]	10305	1			T25	1		T69	3		T71	2
valid_sources[0x28]	10534	1			T27	2		T64	3		T69	2
valid_sources[0x29]	9942	1			T24	2		T25	3		T28	1
valid_sources[0x2a]	9193	1			T24	1		T25	2		T64	2
valid_sources[0x2b]	11335	1			T24	4		T25	5		T27	1
valid_sources[0x2c]	12214	1			T24	3		T25	4		T64	11
valid_sources[0x2d]	13469	1			T23	3		T24	1		T25	3
valid_sources[0x2e]	10028	1			T24	2		T25	1		T27	3
valid_sources[0x2f]	9942	1			T24	1		T25	2		T44	2
valid_sources[0x30]	11052	1			T23	2		T24	1		T25	1
valid_sources[0x31]	10734	1			T24	1		T25	2		T27	1
valid_sources[0x32]	11413	1			T24	6		T25	8		T27	1
valid_sources[0x33]	12838	1			T23	2		T24	7		T25	1
valid_sources[0x34]	10088	1			T24	2		T25	2		T27	4
valid_sources[0x35]	11216	1			T23	3		T27	4		T28	1
valid_sources[0x36]	10216	1			T25	3		T27	5		T67	1
valid_sources[0x37]	10460	1			T24	1		T25	2		T69	1
valid_sources[0x38]	11960	1			T24	1		T25	4		T27	10
valid_sources[0x39]	10540	1			T25	5		T27	5		T69	1
valid_sources[0x3a]	10094	1			T25	4		T27	13		T65	3
valid_sources[0x3b]	11184	1			T24	3		T25	3		T45	1
valid_sources[0x3c]	11320	1			T24	3		T25	2		T27	5
valid_sources[0x3d]	10654	1			T24	2		T25	1		T27	4
valid_sources[0x3e]	9360	1			T25	2		T64	5		T69	4
valid_sources[0x3f]	10125	1			T27	3		T69	5		T71	2
valid_sources[0x40]	9013	1			T24	7		T25	3		T27	7
valid_sources[0x41]	10567	1			T27	3		T69	4		T125	6
valid_sources[0x42]	9516	1			T23	1		T24	2		T25	2
valid_sources[0x43]	10992	1			T24	4		T25	4		T69	1
valid_sources[0x44]	9703	1			T23	1		T24	3		T25	4
valid_sources[0x45]	11339	1			T25	5		T64	4		T65	2
valid_sources[0x46]	9773	1			T25	3		T27	1		T64	1
valid_sources[0x47]	10003	1			T25	3		T64	4		T71	3
valid_sources[0x48]	10371	1			T23	1		T24	2		T25	4
valid_sources[0x49]	11102	1			T25	4		T27	1		T69	2
valid_sources[0x4a]	10261	1			T24	5		T25	4		T27	3
valid_sources[0x4b]	9889	1			T27	1		T65	8		T69	1
valid_sources[0x4c]	10938	1			T24	1		T25	1		T65	1
valid_sources[0x4d]	10218	1			T24	1		T25	1		T27	2
valid_sources[0x4e]	10623	1			T24	6		T25	1		T27	5
valid_sources[0x4f]	8995	1			T24	2		T25	2		T64	8
valid_sources[0x50]	9041	1			T25	1		T28	1		T45	1
valid_sources[0x51]	9618	1			T25	1		T69	6		T80	2
valid_sources[0x52]	10549	1			T23	1		T24	5		T25	3
valid_sources[0x53]	11310	1			T27	1		T28	3		T71	2
valid_sources[0x54]	11146	1			T23	1		T24	7		T25	1
valid_sources[0x55]	11085	1			T24	3		T25	1		T69	2
valid_sources[0x56]	10736	1			T25	1		T64	11		T69	3
valid_sources[0x57]	9556	1			T24	5		T25	3		T28	1
valid_sources[0x58]	12036	1			T25	8		T69	3		T125	13
valid_sources[0x59]	11594	1			T25	3		T64	4		T65	3
valid_sources[0x5a]	11740	1			T24	8		T25	4		T65	1
valid_sources[0x5b]	9836	1			T25	2		T27	18		T64	2
valid_sources[0x5c]	11415	1			T24	2		T25	1		T27	2
valid_sources[0x5d]	9590	1			T24	2		T25	4		T27	2
valid_sources[0x5e]	10351	1			T25	2		T69	3		T71	2
valid_sources[0x5f]	11001	1			T24	3		T25	4		T45	1
valid_sources[0x60]	9745	1			T25	1		T69	4		T71	2
valid_sources[0x61]	10858	1			T24	10		T25	3		T27	1
valid_sources[0x62]	11168	1			T25	3		T27	1		T69	2
valid_sources[0x63]	11707	1			T25	1		T27	2		T64	2
valid_sources[0x64]	11851	1			T24	5		T25	2		T45	1
valid_sources[0x65]	10834	1			T24	3		T25	5		T27	5
valid_sources[0x66]	10365	1			T25	2		T65	1		T69	2
valid_sources[0x67]	10376	1			T23	1		T25	4		T64	1
valid_sources[0x68]	11260	1			T25	4		T29	1		T69	3
valid_sources[0x69]	11239	1			T24	2		T25	1		T27	1
valid_sources[0x6a]	11813	1			T24	5		T25	2		T45	1
valid_sources[0x6b]	10297	1			T23	1		T25	2		T69	2
valid_sources[0x6c]	10174	1			T25	3		T27	1		T29	1
valid_sources[0x6d]	11602	1			T25	1		T65	1		T71	2
valid_sources[0x6e]	9418	1			T24	2		T25	4		T45	1
valid_sources[0x6f]	8898	1			T24	2		T25	1		T27	5
valid_sources[0x70]	9988	1			T24	1		T25	3		T29	1
valid_sources[0x71]	10541	1			T25	1		T27	6		T64	1
valid_sources[0x72]	11394	1			T24	2		T25	3		T45	1
valid_sources[0x73]	12106	1			T25	2		T45	1		T69	3
valid_sources[0x74]	12812	1			T24	1		T69	4		T124	4
valid_sources[0x75]	8808	1			T25	2		T27	3		T28	1
valid_sources[0x76]	10007	1			T24	2		T25	2		T44	1
valid_sources[0x77]	10759	1			T25	1		T27	1		T29	1
valid_sources[0x78]	9580	1			T24	2		T25	1		T27	3
valid_sources[0x79]	9200	1			T25	1		T45	1		T65	5
valid_sources[0x7a]	9855	1			T24	8		T25	4		T27	1
valid_sources[0x7b]	9938	1			T25	1		T27	3		T64	10
valid_sources[0x7c]	9718	1			T24	5		T25	3		T45	1
valid_sources[0x7d]	10624	1			T25	4		T69	2		T71	3
valid_sources[0x7e]	10763	1			T24	3		T25	1		T27	2
valid_sources[0x7f]	9938	1			T24	8		T25	3		T27	8
valid_sources[0x80]	10826	1			T24	5		T25	1		T27	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

550882

1

T23

40

T24

111

T25

86

values[0x0]

all_enables

biggest_size

820589

1

T24

207

T25

140

T27

208

values[0x1]

all_enables

biggest_size

821030

1

T24

197

T25

160

T27

170