Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

6107427

1

T24

734

T25

1842

T27

1165

full_word

2626775

1

T23

40

T24

585

T25

512

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	8733892	1			T23	40		T24	1319		T25	2354
auto[TlIntgErrCmd]	94	1			T46	5		T67	5		T68	4
auto[TlIntgErrData]	121	1			T46	9		T67	12		T68	4
auto[TlIntgErrBoth]	95	1			T46	6		T67	3		T68	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1036056

1

T23

40

T24

158

T25

176

auto[1]

7698146

1

T24

1161

T25

2178

T27

1559

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	432393	1			T24	36		T25	73		T27	44
auto[TlIntgErrNone]	partial	auto[1]	5674751	1			T24	698		T25	1769		T27	1121
auto[TlIntgErrNone]	full_word	auto[0]	603526	1			T23	40		T24	122		T25	103
auto[TlIntgErrNone]	full_word	auto[1]	2023222	1			T24	463		T25	409		T27	438
auto[TlIntgErrCmd]	partial	auto[0]	34	1			T46	1		T68	4		T114	1
auto[TlIntgErrCmd]	partial	auto[1]	53	1			T46	3		T67	5		T116	5
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T120	1		T121	1		T122	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T46	1		T123	1		T117	1
auto[TlIntgErrData]	partial	auto[0]	56	1			T46	3		T67	3		T68	2
auto[TlIntgErrData]	partial	auto[1]	55	1			T46	6		T67	8		T68	2
auto[TlIntgErrData]	full_word	auto[0]	1	1			T121	1		-	-		-	-
auto[TlIntgErrData]	full_word	auto[1]	9	1			T67	1		T113	1		T115	2
auto[TlIntgErrBoth]	partial	auto[0]	38	1			T46	1		T67	1		T68	1
auto[TlIntgErrBoth]	partial	auto[1]	47	1			T46	4		T67	1		T114	5
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T46	1		T68	1		T123	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T67	1		T115	2		T120	1