SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
rom_ctrl_kmac_cg | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 7 | 0 | 7 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_kmac_done | 3 | 0 | 3 | 100.00 | 100 | 1 | 1 | 0 | |
cp_kmac_ready | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 3 | 0 | 3 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
kmac_first | 549 | 1 | T23 | 4 | T28 | 1 | T29 | 1 | ||||
same_cycle | 20 | 1 | T77 | 1 | T124 | 1 | T8 | 1 | ||||
rom_first | 1423 | 1 | T22 | 1 | T23 | 17 | T24 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
stall_repeat | 90377703 | 1 | T22 | 71761 | T23 | 146277 | T24 | 9378 | ||||
stall_long | 9423767 | 1 | T22 | 7410 | T23 | 151760 | T25 | 3103 | ||||
stall_1 | 849451 | 1 | T22 | 146 | T23 | 4110 | T24 | 2028 | ||||
zero_delay_5 | 3635161 | 1 | T24 | 34 | T28 | 9252 | T29 | 3 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |