Line Coverage for Module :
rom_ctrl
| Line No. | Total | Covered | Percent |
TOTAL | | 65 | 65 | 100.00 |
CONT_ASSIGN | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 122 | 1 | 1 | 100.00 |
CONT_ASSIGN | 123 | 1 | 1 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
CONT_ASSIGN | 125 | 1 | 1 | 100.00 |
CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 222 | 1 | 1 | 100.00 |
CONT_ASSIGN | 268 | 1 | 1 | 100.00 |
CONT_ASSIGN | 323 | 1 | 1 | 100.00 |
CONT_ASSIGN | 425 | 1 | 1 | 100.00 |
CONT_ASSIGN | 425 | 1 | 1 | 100.00 |
CONT_ASSIGN | 425 | 1 | 1 | 100.00 |
CONT_ASSIGN | 425 | 1 | 1 | 100.00 |
CONT_ASSIGN | 425 | 1 | 1 | 100.00 |
CONT_ASSIGN | 425 | 1 | 1 | 100.00 |
CONT_ASSIGN | 425 | 1 | 1 | 100.00 |
CONT_ASSIGN | 425 | 1 | 1 | 100.00 |
CONT_ASSIGN | 426 | 1 | 1 | 100.00 |
CONT_ASSIGN | 426 | 1 | 1 | 100.00 |
CONT_ASSIGN | 426 | 1 | 1 | 100.00 |
CONT_ASSIGN | 426 | 1 | 1 | 100.00 |
CONT_ASSIGN | 426 | 1 | 1 | 100.00 |
CONT_ASSIGN | 426 | 1 | 1 | 100.00 |
CONT_ASSIGN | 426 | 1 | 1 | 100.00 |
CONT_ASSIGN | 426 | 1 | 1 | 100.00 |
CONT_ASSIGN | 428 | 1 | 1 | 100.00 |
CONT_ASSIGN | 428 | 1 | 1 | 100.00 |
CONT_ASSIGN | 428 | 1 | 1 | 100.00 |
CONT_ASSIGN | 428 | 1 | 1 | 100.00 |
CONT_ASSIGN | 428 | 1 | 1 | 100.00 |
CONT_ASSIGN | 428 | 1 | 1 | 100.00 |
CONT_ASSIGN | 428 | 1 | 1 | 100.00 |
CONT_ASSIGN | 428 | 1 | 1 | 100.00 |
CONT_ASSIGN | 429 | 1 | 1 | 100.00 |
CONT_ASSIGN | 429 | 1 | 1 | 100.00 |
CONT_ASSIGN | 429 | 1 | 1 | 100.00 |
CONT_ASSIGN | 429 | 1 | 1 | 100.00 |
CONT_ASSIGN | 429 | 1 | 1 | 100.00 |
CONT_ASSIGN | 429 | 1 | 1 | 100.00 |
CONT_ASSIGN | 429 | 1 | 1 | 100.00 |
CONT_ASSIGN | 429 | 1 | 1 | 100.00 |
CONT_ASSIGN | 431 | 1 | 1 | 100.00 |
CONT_ASSIGN | 431 | 1 | 1 | 100.00 |
CONT_ASSIGN | 431 | 1 | 1 | 100.00 |
CONT_ASSIGN | 431 | 1 | 1 | 100.00 |
CONT_ASSIGN | 431 | 1 | 1 | 100.00 |
CONT_ASSIGN | 431 | 1 | 1 | 100.00 |
CONT_ASSIGN | 431 | 1 | 1 | 100.00 |
CONT_ASSIGN | 431 | 1 | 1 | 100.00 |
CONT_ASSIGN | 432 | 1 | 1 | 100.00 |
CONT_ASSIGN | 432 | 1 | 1 | 100.00 |
CONT_ASSIGN | 432 | 1 | 1 | 100.00 |
CONT_ASSIGN | 432 | 1 | 1 | 100.00 |
CONT_ASSIGN | 432 | 1 | 1 | 100.00 |
CONT_ASSIGN | 432 | 1 | 1 | 100.00 |
CONT_ASSIGN | 432 | 1 | 1 | 100.00 |
CONT_ASSIGN | 432 | 1 | 1 | 100.00 |
CONT_ASSIGN | 436 | 1 | 1 | 100.00 |
CONT_ASSIGN | 438 | 1 | 1 | 100.00 |
CONT_ASSIGN | 441 | 1 | 1 | 100.00 |
CONT_ASSIGN | 442 | 1 | 1 | 100.00 |
CONT_ASSIGN | 443 | 1 | 1 | 100.00 |
CONT_ASSIGN | 444 | 1 | 1 | 100.00 |
CONT_ASSIGN | 449 | 1 | 1 | 100.00 |
CONT_ASSIGN | 453 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv' or '../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
117 |
1 |
1 |
122 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
128 |
1 |
1 |
222 |
1 |
1 |
268 |
1 |
1 |
323 |
1 |
1 |
425 |
8 |
8 |
426 |
8 |
8 |
428 |
8 |
8 |
429 |
8 |
8 |
431 |
8 |
8 |
432 |
8 |
8 |
436 |
1 |
1 |
438 |
1 |
1 |
441 |
1 |
1 |
442 |
1 |
1 |
443 |
1 |
1 |
444 |
1 |
1 |
449 |
1 |
1 |
453 |
1 |
1 |
Cond Coverage for Module :
rom_ctrl
| Total | Covered | Percent |
Conditions | 58 | 57 | 98.28 |
Logical | 58 | 57 | 98.28 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 222
EXPRESSION (tl_rom_h2d_upstream.a_valid ? tl_rom_h2d_upstream.a_address[2+:RomIndexWidth] : '0)
-------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T3,T4,T5 |
LINE 268
EXPRESSION (bus_rom_rvalid_raw & ((!internal_alert)))
---------1-------- ---------2---------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T8,T39,T40 |
1 | 1 | Covered | T3,T4,T5 |
LINE 429
EXPRESSION (exp_digest_de && (0[2:0] == exp_digest_idx))
------1------ -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 429
SUB-EXPRESSION (0[2:0] == exp_digest_idx)
-------------1------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 429
EXPRESSION (exp_digest_de && (1[2:0] == exp_digest_idx))
------1------ -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 429
SUB-EXPRESSION (1[2:0] == exp_digest_idx)
-------------1------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 429
EXPRESSION (exp_digest_de && (2[2:0] == exp_digest_idx))
------1------ -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 429
SUB-EXPRESSION (2[2:0] == exp_digest_idx)
-------------1------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 429
EXPRESSION (exp_digest_de && (3[2:0] == exp_digest_idx))
------1------ -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 429
SUB-EXPRESSION (3[2:0] == exp_digest_idx)
-------------1------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 429
EXPRESSION (exp_digest_de && (4[2:0] == exp_digest_idx))
------1------ -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 429
SUB-EXPRESSION (4[2:0] == exp_digest_idx)
-------------1------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 429
EXPRESSION (exp_digest_de && (5[2:0] == exp_digest_idx))
------1------ -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 429
SUB-EXPRESSION (5[2:0] == exp_digest_idx)
-------------1------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 429
EXPRESSION (exp_digest_de && (6[2:0] == exp_digest_idx))
------1------ -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 429
SUB-EXPRESSION (6[2:0] == exp_digest_idx)
-------------1------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 429
EXPRESSION (exp_digest_de && (7[2:0] == exp_digest_idx))
------1------ -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 429
SUB-EXPRESSION (7[2:0] == exp_digest_idx)
-------------1------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 436
EXPRESSION (rom_reg_integrity_error | rom_integrity_error | reg_integrity_error)
-----------1----------- ---------2--------- ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 1 | Covered | T41,T42,T43 |
0 | 1 | 0 | Not Covered | |
1 | 0 | 0 | Unreachable | |
LINE 438
EXPRESSION (checker_alert | mux_alert)
------1------ ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T8,T39,T40 |
1 | 0 | Covered | T1,T8,T20 |
LINE 449
EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
---------1--------- ----------2---------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T6,T9 |
1 | 0 | Covered | T3,T4,T6 |
1 | 1 | Covered | T6,T9,T10 |
LINE 453
EXPRESSION (bus_integrity_error | checker_alert | mux_alert)
---------1--------- ------2------ ----3----
-1- | -2- | -3- | Status | Tests |
0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 1 | Covered | T8,T39,T40 |
0 | 1 | 0 | Covered | T1,T8,T20 |
1 | 0 | 0 | Covered | T41,T42,T43 |
Toggle Coverage for Module :
rom_ctrl
| Total | Covered | Percent |
Totals |
61 |
56 |
91.80 |
Total Bits |
2882 |
2805 |
97.33 |
Total Bits 0->1 |
1441 |
1402 |
97.29 |
Total Bits 1->0 |
1441 |
1403 |
97.36 |
| | | |
Ports |
61 |
56 |
91.80 |
Port Bits |
2882 |
2805 |
97.33 |
Port Bits 0->1 |
1441 |
1402 |
97.29 |
Port Bits 1->0 |
1441 |
1403 |
97.36 |
Port Details
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i |
Yes |
Yes |
T22,T23,T24 |
Yes |
T22,T23,T24 |
INPUT |
rst_ni |
Yes |
Yes |
T23,T28,T29 |
Yes |
T22,T23,T24 |
INPUT |
rom_cfg_i.cfg[3:0] |
No |
No |
|
No |
|
INPUT |
rom_cfg_i.cfg_en |
No |
No |
|
No |
|
INPUT |
rom_tl_i.d_ready |
Yes |
Yes |
T22,T23,T26 |
Yes |
T22,T23,T24 |
INPUT |
rom_tl_i.a_user.data_intg[6:0] |
Yes |
Yes |
T23,T24,T25 |
Yes |
T23,T24,T25 |
INPUT |
rom_tl_i.a_user.cmd_intg[6:0] |
Yes |
Yes |
T23,T24,T25 |
Yes |
T23,T24,T25 |
INPUT |
rom_tl_i.a_user.instr_type[3:0] |
Yes |
Yes |
T24,T25,T27 |
Yes |
T24,T25,T27 |
INPUT |
rom_tl_i.a_user.rsvd[4:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
rom_tl_i.a_data[31:0] |
Yes |
Yes |
T23,T24,T25 |
Yes |
T23,T24,T25 |
INPUT |
rom_tl_i.a_mask[3:0] |
Yes |
Yes |
T24,T25,T27 |
Yes |
T24,T25,T27 |
INPUT |
rom_tl_i.a_address[31:0] |
Yes |
Yes |
T24,T25,T27 |
Yes |
T24,T25,T27 |
INPUT |
rom_tl_i.a_source[7:0] |
Yes |
Yes |
T23,T24,T25 |
Yes |
T23,T24,T25 |
INPUT |
rom_tl_i.a_size[1:0] |
Yes |
Yes |
T24,T25,T27 |
Yes |
T24,T25,T27 |
INPUT |
rom_tl_i.a_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
rom_tl_i.a_opcode[2:0] |
Yes |
Yes |
T24,T25,T27 |
Yes |
T24,T25,T27 |
INPUT |
rom_tl_i.a_valid |
Yes |
Yes |
T23,T24,T25 |
Yes |
T23,T24,T25 |
INPUT |
rom_tl_o.a_ready |
Yes |
Yes |
T23,T28,T29 |
Yes |
T22,T23,T24 |
OUTPUT |
rom_tl_o.d_error |
Yes |
Yes |
T24,T25,T27 |
Yes |
T24,T25,T27 |
OUTPUT |
rom_tl_o.d_user.data_intg[6:0] |
Yes |
Yes |
T23,T29,T44 |
Yes |
T23,T29,T44 |
OUTPUT |
rom_tl_o.d_user.rsp_intg[5:0] |
Yes |
Yes |
*T23,T24,T25 |
Yes |
T23,T24,T25 |
OUTPUT |
rom_tl_o.d_user.rsp_intg[6] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
rom_tl_o.d_data[31:0] |
Yes |
Yes |
T23,T24,T25 |
Yes |
T23,T24,T25 |
OUTPUT |
rom_tl_o.d_sink |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
rom_tl_o.d_source[7:0] |
Yes |
Yes |
T23,T24,T25 |
Yes |
T23,T24,T25 |
OUTPUT |
rom_tl_o.d_size[1:0] |
Yes |
Yes |
T24,T25,T27 |
Yes |
T24,T25,T27 |
OUTPUT |
rom_tl_o.d_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
rom_tl_o.d_opcode[0] |
Yes |
Yes |
*T24,*T25,*T27 |
Yes |
T24,T25,T27 |
OUTPUT |
rom_tl_o.d_opcode[2:1] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
rom_tl_o.d_valid |
Yes |
Yes |
T23,T24,T25 |
Yes |
T23,T24,T25 |
OUTPUT |
regs_tl_i.d_ready |
Yes |
Yes |
T22,T23,T26 |
Yes |
T22,T23,T24 |
INPUT |
regs_tl_i.a_user.data_intg[6:0] |
Yes |
Yes |
T22,T23,T24 |
Yes |
T22,T23,T24 |
INPUT |
regs_tl_i.a_user.cmd_intg[6:0] |
Yes |
Yes |
T22,T23,T24 |
Yes |
T22,T23,T24 |
INPUT |
regs_tl_i.a_user.instr_type[3:0] |
Yes |
Yes |
T23,T24,T25 |
Yes |
T23,T24,T25 |
INPUT |
regs_tl_i.a_user.rsvd[4:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
regs_tl_i.a_data[31:0] |
Yes |
Yes |
T22,T23,T24 |
Yes |
T22,T23,T24 |
INPUT |
regs_tl_i.a_mask[3:0] |
Yes |
Yes |
T22,T23,T24 |
Yes |
T22,T23,T24 |
INPUT |
regs_tl_i.a_address[31:0] |
Yes |
Yes |
T22,T23,T24 |
Yes |
T22,T23,T24 |
INPUT |
regs_tl_i.a_source[7:0] |
Yes |
Yes |
T22,T23,T24 |
Yes |
T22,T23,T24 |
INPUT |
regs_tl_i.a_size[1:0] |
Yes |
Yes |
T22,T23,T24 |
Yes |
T22,T23,T24 |
INPUT |
regs_tl_i.a_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
regs_tl_i.a_opcode[2:0] |
Yes |
Yes |
T22,T23,T24 |
Yes |
T22,T23,T24 |
INPUT |
regs_tl_i.a_valid |
Yes |
Yes |
T22,T23,T24 |
Yes |
T22,T23,T24 |
INPUT |
regs_tl_o.a_ready |
Yes |
Yes |
T22,T23,T24 |
Yes |
T22,T23,T24 |
OUTPUT |
regs_tl_o.d_error |
Yes |
Yes |
T28,T45,T46 |
Yes |
T24,T25,T27 |
OUTPUT |
regs_tl_o.d_user.data_intg[6:0] |
Yes |
Yes |
T1,T3,T4 |
Yes |
T1,T3,T4 |
OUTPUT |
regs_tl_o.d_user.rsp_intg[5:0] |
Yes |
Yes |
*T22,*T23,*T24 |
Yes |
T22,T23,T24 |
OUTPUT |
regs_tl_o.d_user.rsp_intg[6] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
regs_tl_o.d_data[31:0] |
Yes |
Yes |
T22,T23,T26 |
Yes |
T22,T23,T24 |
OUTPUT |
regs_tl_o.d_sink |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
regs_tl_o.d_source[7:0] |
Yes |
Yes |
T22,T23,T24 |
Yes |
T22,T23,T24 |
OUTPUT |
regs_tl_o.d_size[1:0] |
Yes |
Yes |
T22,T23,T24 |
Yes |
T22,T23,T24 |
OUTPUT |
regs_tl_o.d_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
regs_tl_o.d_opcode[0] |
Yes |
Yes |
*T22,*T23,*T24 |
Yes |
T22,T23,T24 |
OUTPUT |
regs_tl_o.d_opcode[2:1] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
regs_tl_o.d_valid |
Yes |
Yes |
T22,T23,T24 |
Yes |
T22,T23,T24 |
OUTPUT |
alert_rx_i[0].ack_n |
Yes |
Yes |
T22,T23,T24 |
Yes |
T22,T23,T24 |
INPUT |
alert_rx_i[0].ack_p |
Yes |
Yes |
T22,T23,T29 |
Yes |
T22,T23,T29 |
INPUT |
alert_rx_i[0].ping_n |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
alert_rx_i[0].ping_p |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
alert_tx_o[0].alert_n |
Yes |
Yes |
T22,T23,T24 |
Yes |
T22,T23,T24 |
OUTPUT |
alert_tx_o[0].alert_p |
Yes |
Yes |
T22,T23,T29 |
Yes |
T22,T23,T29 |
OUTPUT |
pwrmgr_data_o.good[3:0] |
Yes |
Yes |
T22,T23,T24 |
Yes |
T22,T23,T24 |
OUTPUT |
pwrmgr_data_o.done[3:0] |
Yes |
Yes |
T22,T23,T24 |
Yes |
T23,T29,T44 |
OUTPUT |
keymgr_data_o.valid |
Yes |
Yes |
T23,T29,T44 |
Yes |
T22,T23,T24 |
OUTPUT |
keymgr_data_o.data[255:0] |
Yes |
Yes |
T23,T29,T44 |
Yes |
T23,T24,T29 |
OUTPUT |
kmac_data_i.error |
No |
Yes |
T1,T20,T37 |
No |
|
INPUT |
kmac_data_i.digest_share1[383:0] |
Yes |
Yes |
T23,T29,T44 |
Yes |
T23,T29,T44 |
INPUT |
kmac_data_i.digest_share0[383:0] |
Yes |
Yes |
T23,T29,T44 |
Yes |
T23,T29,T44 |
INPUT |
kmac_data_i.done |
Yes |
Yes |
T22,T23,T24 |
Yes |
T22,T23,T24 |
INPUT |
kmac_data_i.ready |
Yes |
Yes |
T22,T23,T24 |
Yes |
T22,T23,T24 |
INPUT |
kmac_data_o.last |
Yes |
Yes |
T22,T23,T24 |
Yes |
T22,T23,T24 |
OUTPUT |
kmac_data_o.strb[7:0] |
No |
No |
|
No |
|
OUTPUT |
kmac_data_o.data[38:0] |
Yes |
Yes |
T22,T23,T24 |
Yes |
T22,T23,T24 |
OUTPUT |
kmac_data_o.data[63:39] |
No |
No |
|
No |
|
OUTPUT |
kmac_data_o.valid |
Yes |
Yes |
T22,T23,T24 |
Yes |
T22,T23,T24 |
OUTPUT |
*Tests covering at least one bit in the range
Branch Coverage for Module :
rom_ctrl
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
TERNARY |
222 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv' or '../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 222 (tl_rom_h2d_upstream.a_valid) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T3,T4,T5 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
rom_ctrl
Assertion Details
AlertTxOKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
262941156 |
262766665 |
0 |
0 |
T1 |
16762 |
16578 |
0 |
0 |
T2 |
8486 |
8424 |
0 |
0 |
T3 |
302831 |
302670 |
0 |
0 |
T4 |
336573 |
336435 |
0 |
0 |
T5 |
457394 |
457034 |
0 |
0 |
T6 |
8541 |
8484 |
0 |
0 |
T7 |
9060 |
8976 |
0 |
0 |
T8 |
515604 |
512745 |
0 |
0 |
T9 |
8402 |
8336 |
0 |
0 |
T10 |
211855 |
211771 |
0 |
0 |
BusRomIndicesMatch_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
262918878 |
262752424 |
0 |
0 |
T1 |
16762 |
16578 |
0 |
0 |
T2 |
8486 |
8424 |
0 |
0 |
T3 |
302831 |
302670 |
0 |
0 |
T4 |
336573 |
336435 |
0 |
0 |
T5 |
457394 |
457034 |
0 |
0 |
T6 |
8541 |
8484 |
0 |
0 |
T7 |
9060 |
8976 |
0 |
0 |
T8 |
515530 |
512725 |
0 |
0 |
T9 |
8402 |
8336 |
0 |
0 |
T10 |
211855 |
211771 |
0 |
0 |
FpvSecCmFifoRptrCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
262941156 |
0 |
0 |
0 |
FpvSecCmFifoWptrCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
262941156 |
0 |
0 |
0 |
FpvSecCmRegWeOnehotCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
262941156 |
60 |
0 |
0 |
T41 |
190055 |
10 |
0 |
0 |
T42 |
109997 |
10 |
0 |
0 |
T43 |
0 |
10 |
0 |
0 |
T47 |
0 |
10 |
0 |
0 |
T48 |
0 |
20 |
0 |
0 |
T49 |
8430 |
0 |
0 |
0 |
T50 |
150386 |
0 |
0 |
0 |
T51 |
205980 |
0 |
0 |
0 |
T52 |
176223 |
0 |
0 |
0 |
T53 |
18279 |
0 |
0 |
0 |
T54 |
30613 |
0 |
0 |
0 |
T55 |
16636 |
0 |
0 |
0 |
T56 |
255033 |
0 |
0 |
0 |
KeymgrDataODataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
262941156 |
106898357 |
0 |
0 |
T1 |
16762 |
131 |
0 |
0 |
T2 |
8486 |
219 |
0 |
0 |
T3 |
302831 |
1288 |
0 |
0 |
T4 |
336573 |
1469 |
0 |
0 |
T5 |
457394 |
3022 |
0 |
0 |
T6 |
8541 |
279 |
0 |
0 |
T7 |
9060 |
771 |
0 |
0 |
T8 |
515604 |
5704 |
0 |
0 |
T9 |
8402 |
131 |
0 |
0 |
T10 |
211855 |
13 |
0 |
0 |
KeymgrDataODataKnown_AKnownEnable
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
262941156 |
262766665 |
0 |
0 |
T1 |
16762 |
16578 |
0 |
0 |
T2 |
8486 |
8424 |
0 |
0 |
T3 |
302831 |
302670 |
0 |
0 |
T4 |
336573 |
336435 |
0 |
0 |
T5 |
457394 |
457034 |
0 |
0 |
T6 |
8541 |
8484 |
0 |
0 |
T7 |
9060 |
8976 |
0 |
0 |
T8 |
515604 |
512745 |
0 |
0 |
T9 |
8402 |
8336 |
0 |
0 |
T10 |
211855 |
211771 |
0 |
0 |
KeymgrDataOValidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
262941156 |
262766665 |
0 |
0 |
T1 |
16762 |
16578 |
0 |
0 |
T2 |
8486 |
8424 |
0 |
0 |
T3 |
302831 |
302670 |
0 |
0 |
T4 |
336573 |
336435 |
0 |
0 |
T5 |
457394 |
457034 |
0 |
0 |
T6 |
8541 |
8484 |
0 |
0 |
T7 |
9060 |
8976 |
0 |
0 |
T8 |
515604 |
512745 |
0 |
0 |
T9 |
8402 |
8336 |
0 |
0 |
T10 |
211855 |
211771 |
0 |
0 |
KeymgrValidChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
262941156 |
0 |
0 |
337 |
KmacDataODataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
262941156 |
155731414 |
0 |
0 |
T1 |
16762 |
16368 |
0 |
0 |
T2 |
8486 |
8184 |
0 |
0 |
T3 |
302831 |
301158 |
0 |
0 |
T4 |
336573 |
334848 |
0 |
0 |
T5 |
457394 |
453789 |
0 |
0 |
T6 |
8541 |
8184 |
0 |
0 |
T7 |
9060 |
8184 |
0 |
0 |
T8 |
515604 |
505456 |
0 |
0 |
T9 |
8402 |
8184 |
0 |
0 |
T10 |
211855 |
211728 |
0 |
0 |
KmacDataODataKnown_AKnownEnable
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
262941156 |
262766665 |
0 |
0 |
T1 |
16762 |
16578 |
0 |
0 |
T2 |
8486 |
8424 |
0 |
0 |
T3 |
302831 |
302670 |
0 |
0 |
T4 |
336573 |
336435 |
0 |
0 |
T5 |
457394 |
457034 |
0 |
0 |
T6 |
8541 |
8484 |
0 |
0 |
T7 |
9060 |
8976 |
0 |
0 |
T8 |
515604 |
512745 |
0 |
0 |
T9 |
8402 |
8336 |
0 |
0 |
T10 |
211855 |
211771 |
0 |
0 |
KmacDataOValidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
262941156 |
262766665 |
0 |
0 |
T1 |
16762 |
16578 |
0 |
0 |
T2 |
8486 |
8424 |
0 |
0 |
T3 |
302831 |
302670 |
0 |
0 |
T4 |
336573 |
336435 |
0 |
0 |
T5 |
457394 |
457034 |
0 |
0 |
T6 |
8541 |
8484 |
0 |
0 |
T7 |
9060 |
8976 |
0 |
0 |
T8 |
515604 |
512745 |
0 |
0 |
T9 |
8402 |
8336 |
0 |
0 |
T10 |
211855 |
211771 |
0 |
0 |
PwrmgrDataChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
262941156 |
0 |
0 |
337 |
PwrmgrDataOKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
262941156 |
262766665 |
0 |
0 |
T1 |
16762 |
16578 |
0 |
0 |
T2 |
8486 |
8424 |
0 |
0 |
T3 |
302831 |
302670 |
0 |
0 |
T4 |
336573 |
336435 |
0 |
0 |
T5 |
457394 |
457034 |
0 |
0 |
T6 |
8541 |
8484 |
0 |
0 |
T7 |
9060 |
8976 |
0 |
0 |
T8 |
515604 |
512745 |
0 |
0 |
T9 |
8402 |
8336 |
0 |
0 |
T10 |
211855 |
211771 |
0 |
0 |
RegsTlOAReadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
262941156 |
262766665 |
0 |
0 |
T1 |
16762 |
16578 |
0 |
0 |
T2 |
8486 |
8424 |
0 |
0 |
T3 |
302831 |
302670 |
0 |
0 |
T4 |
336573 |
336435 |
0 |
0 |
T5 |
457394 |
457034 |
0 |
0 |
T6 |
8541 |
8484 |
0 |
0 |
T7 |
9060 |
8976 |
0 |
0 |
T8 |
515604 |
512745 |
0 |
0 |
T9 |
8402 |
8336 |
0 |
0 |
T10 |
211855 |
211771 |
0 |
0 |
RegsTlODDataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
262941156 |
14673051 |
0 |
0 |
T1 |
16762 |
1 |
0 |
0 |
T2 |
8486 |
1 |
0 |
0 |
T3 |
302831 |
32 |
0 |
0 |
T4 |
336573 |
32 |
0 |
0 |
T5 |
457394 |
308 |
0 |
0 |
T6 |
8541 |
14 |
0 |
0 |
T7 |
9060 |
0 |
0 |
0 |
T8 |
515604 |
35 |
0 |
0 |
T9 |
8402 |
9 |
0 |
0 |
T10 |
211855 |
80 |
0 |
0 |
T20 |
0 |
1 |
0 |
0 |
RegsTlODDataKnown_AKnownEnable
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
262941156 |
262766665 |
0 |
0 |
T1 |
16762 |
16578 |
0 |
0 |
T2 |
8486 |
8424 |
0 |
0 |
T3 |
302831 |
302670 |
0 |
0 |
T4 |
336573 |
336435 |
0 |
0 |
T5 |
457394 |
457034 |
0 |
0 |
T6 |
8541 |
8484 |
0 |
0 |
T7 |
9060 |
8976 |
0 |
0 |
T8 |
515604 |
512745 |
0 |
0 |
T9 |
8402 |
8336 |
0 |
0 |
T10 |
211855 |
211771 |
0 |
0 |
RegsTlODValidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
262941156 |
262766665 |
0 |
0 |
T1 |
16762 |
16578 |
0 |
0 |
T2 |
8486 |
8424 |
0 |
0 |
T3 |
302831 |
302670 |
0 |
0 |
T4 |
336573 |
336435 |
0 |
0 |
T5 |
457394 |
457034 |
0 |
0 |
T6 |
8541 |
8484 |
0 |
0 |
T7 |
9060 |
8976 |
0 |
0 |
T8 |
515604 |
512745 |
0 |
0 |
T9 |
8402 |
8336 |
0 |
0 |
T10 |
211855 |
211771 |
0 |
0 |
RomTlOAReadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
262941156 |
262766665 |
0 |
0 |
T1 |
16762 |
16578 |
0 |
0 |
T2 |
8486 |
8424 |
0 |
0 |
T3 |
302831 |
302670 |
0 |
0 |
T4 |
336573 |
336435 |
0 |
0 |
T5 |
457394 |
457034 |
0 |
0 |
T6 |
8541 |
8484 |
0 |
0 |
T7 |
9060 |
8976 |
0 |
0 |
T8 |
515604 |
512745 |
0 |
0 |
T9 |
8402 |
8336 |
0 |
0 |
T10 |
211855 |
211771 |
0 |
0 |
RomTlODDataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
262941156 |
15748255 |
0 |
0 |
T3 |
302831 |
346 |
0 |
0 |
T4 |
336573 |
276 |
0 |
0 |
T5 |
457394 |
150 |
0 |
0 |
T6 |
8541 |
0 |
0 |
0 |
T7 |
9060 |
62 |
0 |
0 |
T8 |
515604 |
13 |
0 |
0 |
T9 |
8402 |
0 |
0 |
0 |
T10 |
211855 |
0 |
0 |
0 |
T11 |
0 |
353254 |
0 |
0 |
T12 |
0 |
161775 |
0 |
0 |
T17 |
0 |
493 |
0 |
0 |
T18 |
0 |
262 |
0 |
0 |
T19 |
0 |
390 |
0 |
0 |
T20 |
238871 |
0 |
0 |
0 |
T21 |
82179 |
0 |
0 |
0 |
RomTlODDataKnown_AKnownEnable
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
262941156 |
262766665 |
0 |
0 |
T1 |
16762 |
16578 |
0 |
0 |
T2 |
8486 |
8424 |
0 |
0 |
T3 |
302831 |
302670 |
0 |
0 |
T4 |
336573 |
336435 |
0 |
0 |
T5 |
457394 |
457034 |
0 |
0 |
T6 |
8541 |
8484 |
0 |
0 |
T7 |
9060 |
8976 |
0 |
0 |
T8 |
515604 |
512745 |
0 |
0 |
T9 |
8402 |
8336 |
0 |
0 |
T10 |
211855 |
211771 |
0 |
0 |
RomTlODValidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
262941156 |
262766665 |
0 |
0 |
T1 |
16762 |
16578 |
0 |
0 |
T2 |
8486 |
8424 |
0 |
0 |
T3 |
302831 |
302670 |
0 |
0 |
T4 |
336573 |
336435 |
0 |
0 |
T5 |
457394 |
457034 |
0 |
0 |
T6 |
8541 |
8484 |
0 |
0 |
T7 |
9060 |
8976 |
0 |
0 |
T8 |
515604 |
512745 |
0 |
0 |
T9 |
8402 |
8336 |
0 |
0 |
T10 |
211855 |
211771 |
0 |
0 |
StabilityChkKmac_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
262941156 |
155728904 |
0 |
0 |
T1 |
16762 |
16366 |
0 |
0 |
T2 |
8486 |
8183 |
0 |
0 |
T3 |
302831 |
301156 |
0 |
0 |
T4 |
336573 |
334846 |
0 |
0 |
T5 |
457394 |
453784 |
0 |
0 |
T6 |
8541 |
8183 |
0 |
0 |
T7 |
9060 |
8183 |
0 |
0 |
T8 |
515604 |
505418 |
0 |
0 |
T9 |
8402 |
8183 |
0 |
0 |
T10 |
211855 |
211727 |
0 |
0 |
StabilityChkkeymgr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
262941156 |
106897033 |
0 |
0 |
T1 |
16762 |
130 |
0 |
0 |
T2 |
8486 |
218 |
0 |
0 |
T3 |
302831 |
1286 |
0 |
0 |
T4 |
336573 |
1467 |
0 |
0 |
T5 |
457394 |
3018 |
0 |
0 |
T6 |
8541 |
278 |
0 |
0 |
T7 |
9060 |
770 |
0 |
0 |
T8 |
515604 |
5688 |
0 |
0 |
T9 |
8402 |
130 |
0 |
0 |
T10 |
211855 |
12 |
0 |
0 |
TlAccessChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
262941156 |
155868308 |
0 |
0 |
T1 |
16762 |
16447 |
0 |
0 |
T2 |
8486 |
8205 |
0 |
0 |
T3 |
302831 |
301382 |
0 |
0 |
T4 |
336573 |
334966 |
0 |
0 |
T5 |
457394 |
454012 |
0 |
0 |
T6 |
8541 |
8205 |
0 |
0 |
T7 |
9060 |
8205 |
0 |
0 |
T8 |
515604 |
507041 |
0 |
0 |
T9 |
8402 |
8205 |
0 |
0 |
T10 |
211855 |
211758 |
0 |
0 |
gen_asserts_with_scrambling.FpvSecCmCheckerFsmAlert_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
262941156 |
60 |
0 |
0 |
T41 |
190055 |
10 |
0 |
0 |
T42 |
109997 |
10 |
0 |
0 |
T43 |
0 |
10 |
0 |
0 |
T47 |
0 |
10 |
0 |
0 |
T48 |
0 |
20 |
0 |
0 |
T49 |
8430 |
0 |
0 |
0 |
T50 |
150386 |
0 |
0 |
0 |
T51 |
205980 |
0 |
0 |
0 |
T52 |
176223 |
0 |
0 |
0 |
T53 |
18279 |
0 |
0 |
0 |
T54 |
30613 |
0 |
0 |
0 |
T55 |
16636 |
0 |
0 |
0 |
T56 |
255033 |
0 |
0 |
0 |
gen_asserts_with_scrambling.FpvSecCmCompareAddrCtrCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
262941156 |
0 |
0 |
0 |
gen_asserts_with_scrambling.FpvSecCmCompareFsmAlert_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
262941156 |
495 |
0 |
0 |
T8 |
515604 |
5 |
0 |
0 |
T9 |
8402 |
0 |
0 |
0 |
T10 |
211855 |
0 |
0 |
0 |
T11 |
331477 |
0 |
0 |
0 |
T12 |
317402 |
0 |
0 |
0 |
T17 |
408137 |
0 |
0 |
0 |
T18 |
195928 |
0 |
0 |
0 |
T19 |
222499 |
0 |
0 |
0 |
T20 |
238871 |
0 |
0 |
0 |
T21 |
82179 |
0 |
0 |
0 |
T39 |
0 |
10 |
0 |
0 |
T40 |
0 |
5 |
0 |
0 |
T57 |
0 |
5 |
0 |
0 |
T58 |
0 |
15 |
0 |
0 |
T59 |
0 |
5 |
0 |
0 |
T60 |
0 |
5 |
0 |
0 |
T61 |
0 |
11 |
0 |
0 |
T62 |
0 |
10 |
0 |
0 |
T63 |
0 |
10 |
0 |
0 |
gen_fsm_scramble_enabled_asserts.BusLocalEscChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
262941156 |
0 |
0 |
0 |