Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_rom_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0



Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_rom_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_rom_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_rom_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_rom_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 205619 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 2104685 1 T20 366 T28 350 T29 17



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 575397 1 T20 91 T28 50 T29 2
values[0x0] 802303 1 T20 135 T28 180 T29 6
values[0x1] 932604 1 T20 147 T28 176 T29 12



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 90974 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 2219330 1 T20 369 T28 368 T29 17



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 8675 1 T20 2 T31 1 T42 3
valid_sources[0x01] 9106 1 T20 2 T32 3 T33 1
valid_sources[0x02] 9253 1 T20 3 T31 1 T42 1
valid_sources[0x03] 9023 1 T20 1 T31 2 T32 2
valid_sources[0x04] 9346 1 T20 3 T42 1 T44 1
valid_sources[0x05] 9165 1 T20 1 T31 4 T32 4
valid_sources[0x06] 8497 1 T20 1 T31 3 T32 3
valid_sources[0x07] 9125 1 T20 2 T33 6 T36 5
valid_sources[0x08] 9408 1 T20 5 T30 1 T32 2
valid_sources[0x09] 9143 1 T20 1 T31 1 T32 2
valid_sources[0x0a] 9161 1 T20 2 T31 1 T32 2
valid_sources[0x0b] 8776 1 T20 1 T28 4 T31 2
valid_sources[0x0c] 9027 1 T20 2 T28 6 T30 1
valid_sources[0x0d] 8617 1 T36 6 T60 10 T61 3
valid_sources[0x0e] 9343 1 T20 1 T36 1 T42 1
valid_sources[0x0f] 9480 1 T20 3 T28 9 T31 1
valid_sources[0x10] 8657 1 T20 1 T32 2 T33 2
valid_sources[0x11] 8946 1 T20 3 T28 3 T31 2
valid_sources[0x12] 8683 1 T20 3 T28 5 T31 2
valid_sources[0x13] 8288 1 T20 2 T31 1 T32 5
valid_sources[0x14] 9432 1 T28 11 T32 4 T33 5
valid_sources[0x15] 8627 1 T20 1 T31 1 T32 2
valid_sources[0x16] 8793 1 T20 1 T31 4 T32 1
valid_sources[0x17] 10207 1 T20 2 T28 36 T31 1
valid_sources[0x18] 9096 1 T20 1 T32 2 T33 1
valid_sources[0x19] 8858 1 T20 1 T28 10 T32 3
valid_sources[0x1a] 9818 1 T20 1 T33 1 T42 1
valid_sources[0x1b] 8765 1 T28 22 T31 1 T32 3
valid_sources[0x1c] 8645 1 T20 1 T32 1 T35 10
valid_sources[0x1d] 8724 1 T20 3 T31 3 T32 2
valid_sources[0x1e] 9056 1 T20 1 T28 4 T31 1
valid_sources[0x1f] 9313 1 T20 1 T28 5 T31 1
valid_sources[0x20] 9525 1 T20 2 T32 4 T33 2
valid_sources[0x21] 9129 1 T20 3 T28 3 T30 1
valid_sources[0x22] 9074 1 T20 2 T31 1 T32 2
valid_sources[0x23] 8387 1 T20 2 T32 1 T33 1
valid_sources[0x24] 9450 1 T20 2 T31 1 T32 2
valid_sources[0x25] 9325 1 T28 1 T31 1 T32 1
valid_sources[0x26] 9054 1 T32 1 T33 2 T44 1
valid_sources[0x27] 9309 1 T30 1 T31 2 T32 3
valid_sources[0x28] 8687 1 T20 3 T31 1 T32 1
valid_sources[0x29] 9023 1 T31 1 T32 2 T36 3
valid_sources[0x2a] 8858 1 T20 1 T30 1 T31 1
valid_sources[0x2b] 9329 1 T20 4 T32 1 T33 6
valid_sources[0x2c] 8227 1 T60 4 T42 1 T44 2
valid_sources[0x2d] 9314 1 T20 1 T33 1 T36 4
valid_sources[0x2e] 8821 1 T32 3 T36 3 T42 1
valid_sources[0x2f] 9294 1 T20 1 T31 2 T32 1
valid_sources[0x30] 8772 1 T20 2 T28 3 T31 2
valid_sources[0x31] 9968 1 T31 1 T44 3 T87 13
valid_sources[0x32] 8284 1 T20 2 T36 1 T42 1
valid_sources[0x33] 9081 1 T28 10 T31 1 T32 4
valid_sources[0x34] 8901 1 T20 1 T32 1 T44 4
valid_sources[0x35] 8594 1 T20 1 T28 15 T32 1
valid_sources[0x36] 9547 1 T32 3 T33 1 T42 1
valid_sources[0x37] 8972 1 T20 1 T33 1 T42 2
valid_sources[0x38] 9079 1 T20 2 T32 3 T33 4
valid_sources[0x39] 8416 1 T20 2 T31 1 T32 1
valid_sources[0x3a] 8805 1 T20 1 T32 4 T33 4
valid_sources[0x3b] 8444 1 T20 1 T28 4 T31 1
valid_sources[0x3c] 8483 1 T20 1 T30 1 T32 2
valid_sources[0x3d] 8764 1 T31 4 T42 1 T61 2
valid_sources[0x3e] 8718 1 T20 1 T32 5 T33 4
valid_sources[0x3f] 9064 1 T28 18 T31 1 T33 2
valid_sources[0x40] 8852 1 T31 1 T33 3 T36 2
valid_sources[0x41] 9442 1 T20 1 T42 1 T61 1
valid_sources[0x42] 9518 1 T31 3 T42 1 T61 2
valid_sources[0x43] 9182 1 T20 1 T30 1 T32 1
valid_sources[0x44] 9120 1 T32 1 T62 1 T44 1
valid_sources[0x45] 8298 1 T20 1 T28 8 T31 1
valid_sources[0x46] 9318 1 T28 2 T32 3 T44 1
valid_sources[0x47] 8600 1 T20 2 T30 1 T32 1
valid_sources[0x48] 8275 1 T20 2 T31 1 T32 1
valid_sources[0x49] 8802 1 T20 6 T31 1 T32 3
valid_sources[0x4a] 9292 1 T29 10 T31 3 T32 4
valid_sources[0x4b] 9235 1 T20 5 T31 3 T32 2
valid_sources[0x4c] 8967 1 T20 2 T31 1 T42 2
valid_sources[0x4d] 9297 1 T31 1 T32 4 T36 3
valid_sources[0x4e] 9537 1 T31 1 T32 9 T33 2
valid_sources[0x4f] 9195 1 T20 3 T31 1 T32 2
valid_sources[0x50] 8595 1 T32 1 T33 1 T35 20
valid_sources[0x51] 9082 1 T20 6 T31 1 T32 3
valid_sources[0x52] 8592 1 T20 5 T31 2 T36 1
valid_sources[0x53] 9040 1 T30 2 T36 1 T42 1
valid_sources[0x54] 9600 1 T20 1 T32 3 T34 2
valid_sources[0x55] 9043 1 T20 4 T32 2 T44 2
valid_sources[0x56] 9369 1 T20 1 T32 2 T34 1
valid_sources[0x57] 8685 1 T20 2 T44 1 T54 1
valid_sources[0x58] 9044 1 T20 3 T31 1 T32 1
valid_sources[0x59] 8514 1 T20 1 T30 1 T31 1
valid_sources[0x5a] 8603 1 T20 1 T31 1 T32 1
valid_sources[0x5b] 8973 1 T28 9 T32 2 T36 5
valid_sources[0x5c] 8783 1 T31 2 T32 1 T60 12
valid_sources[0x5d] 8971 1 T31 1 T32 3 T33 1
valid_sources[0x5e] 8447 1 T20 2 T33 3 T44 2
valid_sources[0x5f] 8822 1 T31 1 T32 1 T36 1
valid_sources[0x60] 8849 1 T28 3 T32 2 T42 1
valid_sources[0x61] 8963 1 T20 1 T32 1 T36 2
valid_sources[0x62] 8830 1 T36 1 T44 3 T86 2
valid_sources[0x63] 8697 1 T31 1 T32 7 T33 3
valid_sources[0x64] 9337 1 T20 5 T32 2 T44 2
valid_sources[0x65] 8658 1 T33 1 T42 1 T61 1
valid_sources[0x66] 8520 1 T20 2 T31 3 T32 1
valid_sources[0x67] 8919 1 T20 3 T31 3 T32 2
valid_sources[0x68] 9140 1 T20 3 T28 17 T32 2
valid_sources[0x69] 9181 1 T20 1 T31 1 T33 7
valid_sources[0x6a] 8579 1 T31 1 T32 3 T56 3
valid_sources[0x6b] 9592 1 T20 1 T32 2 T33 1
valid_sources[0x6c] 9066 1 T20 2 T31 4 T33 2
valid_sources[0x6d] 9936 1 T29 10 T31 3 T32 2
valid_sources[0x6e] 8820 1 T20 1 T31 1 T33 1
valid_sources[0x6f] 8039 1 T20 2 T28 6 T32 3
valid_sources[0x70] 8516 1 T20 2 T28 6 T32 2
valid_sources[0x71] 8684 1 T20 2 T28 21 T31 1
valid_sources[0x72] 9591 1 T20 1 T30 1 T42 2
valid_sources[0x73] 10458 1 T20 1 T33 5 T36 3
valid_sources[0x74] 8971 1 T20 5 T28 11 T31 1
valid_sources[0x75] 9099 1 T20 2 T28 6 T31 2
valid_sources[0x76] 9161 1 T20 1 T32 3 T33 9
valid_sources[0x77] 9655 1 T20 1 T31 1 T32 1
valid_sources[0x78] 9397 1 T20 2 T28 18 T31 2
valid_sources[0x79] 8945 1 T20 3 T31 1 T32 1
valid_sources[0x7a] 8438 1 T20 2 T31 1 T32 1
valid_sources[0x7b] 8078 1 T20 3 T32 2 T34 1
valid_sources[0x7c] 8666 1 T20 1 T31 3 T32 6
valid_sources[0x7d] 8617 1 T20 1 T32 1 T36 1
valid_sources[0x7e] 8663 1 T20 1 T31 3 T32 1
valid_sources[0x7f] 8524 1 T61 1 T74 7 T56 5
valid_sources[0x80] 9816 1 T28 5 T31 4 T36 4



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 531874 1 T20 89 T28 12 T29 1
values[0x0] all_enables biggest_size 786028 1 T20 135 T28 174 T29 6
values[0x1] all_enables biggest_size 786783 1 T20 142 T28 164 T29 10


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 467294 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 2051939 1 T20 205 T28 40 T32 417



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 564642 1 T20 45 T28 40 T32 109
values[0x0] 807917 1 T20 80 T32 160 T33 1
values[0x1] 1146674 1 T20 105 T32 206 T33 1



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 177815 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 2341418 1 T20 223 T28 40 T32 451



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 11389 1 T32 1 T42 4 T56 2
valid_sources[0x01] 10796 1 T32 3 T36 40 T53 1
valid_sources[0x02] 9401 1 T32 2 T42 2 T53 5
valid_sources[0x03] 9744 1 T32 2 T42 12 T56 4
valid_sources[0x04] 9957 1 T32 4 T53 1 T58 2
valid_sources[0x05] 9153 1 T20 3 T32 3 T54 1
valid_sources[0x06] 11167 1 T32 2 T53 1 T54 1
valid_sources[0x07] 8874 1 T32 1 T42 3 T54 2
valid_sources[0x08] 9813 1 T54 2 T56 1 T58 3
valid_sources[0x09] 9334 1 T32 3 T58 4 T59 1
valid_sources[0x0a] 10485 1 T32 5 T54 2 T59 3
valid_sources[0x0b] 9905 1 T42 2 T53 1 T54 1
valid_sources[0x0c] 9315 1 T53 1 T54 2 T56 4
valid_sources[0x0d] 9398 1 T20 1 T32 3 T53 6
valid_sources[0x0e] 10001 1 T32 3 T42 1 T54 1
valid_sources[0x0f] 10078 1 T28 1 T32 5 T56 3
valid_sources[0x10] 9257 1 T32 1 T54 1 T56 5
valid_sources[0x11] 9855 1 T32 1 T33 1 T42 2
valid_sources[0x12] 10098 1 T32 2 T53 4 T56 4
valid_sources[0x13] 10350 1 T32 2 T42 2 T56 3
valid_sources[0x14] 9127 1 T32 1 T42 2 T54 2
valid_sources[0x15] 9979 1 T42 1 T54 1 T56 1
valid_sources[0x16] 10631 1 T32 2 T54 1 T56 1
valid_sources[0x17] 8981 1 T42 2 T54 1 T59 2
valid_sources[0x18] 9122 1 T28 1 T32 1 T42 2
valid_sources[0x19] 11877 1 T42 1 T58 1 T59 3
valid_sources[0x1a] 11018 1 T32 3 T42 1 T53 2
valid_sources[0x1b] 9425 1 T20 10 T32 2 T53 5
valid_sources[0x1c] 11803 1 T20 2 T32 3 T53 1
valid_sources[0x1d] 9216 1 T20 3 T32 5 T42 1
valid_sources[0x1e] 8765 1 T28 1 T32 3 T54 2
valid_sources[0x1f] 9169 1 T20 2 T32 1 T54 1
valid_sources[0x20] 10158 1 T32 6 T42 11 T53 3
valid_sources[0x21] 9858 1 T32 2 T53 1 T54 1
valid_sources[0x22] 9907 1 T32 1 T42 1 T53 10
valid_sources[0x23] 11010 1 T32 1 T42 1 T54 2
valid_sources[0x24] 9196 1 T32 2 T42 3 T54 1
valid_sources[0x25] 8963 1 T32 4 T53 2 T54 2
valid_sources[0x26] 9525 1 T32 3 T56 1 T64 9
valid_sources[0x27] 9401 1 T32 2 T42 11 T53 2
valid_sources[0x28] 9715 1 T42 1 T54 2 T58 3
valid_sources[0x29] 10790 1 T32 1 T42 2 T53 2
valid_sources[0x2a] 8980 1 T32 4 T42 1 T56 2
valid_sources[0x2b] 10442 1 T32 1 T42 3 T53 1
valid_sources[0x2c] 9731 1 T32 1 T42 4 T58 1
valid_sources[0x2d] 11656 1 T28 2 T32 2 T42 2
valid_sources[0x2e] 9833 1 T32 2 T53 1 T58 1
valid_sources[0x2f] 9599 1 T32 5 T54 1 T58 2
valid_sources[0x30] 9437 1 T32 2 T56 3 T58 1
valid_sources[0x31] 8776 1 T54 1 T56 1 T59 1
valid_sources[0x32] 9890 1 T56 3 T58 1 T65 1
valid_sources[0x33] 9967 1 T32 1 T54 1 T58 1
valid_sources[0x34] 8719 1 T42 4 T58 1 T71 2
valid_sources[0x35] 9476 1 T53 2 T54 1 T56 8
valid_sources[0x36] 9357 1 T20 1 T32 2 T42 3
valid_sources[0x37] 10116 1 T32 4 T54 1 T56 2
valid_sources[0x38] 10549 1 T32 3 T42 4 T53 5
valid_sources[0x39] 9730 1 T32 2 T42 5 T56 6
valid_sources[0x3a] 9355 1 T32 2 T42 3 T56 3
valid_sources[0x3b] 9935 1 T32 4 T42 2 T54 2
valid_sources[0x3c] 9149 1 T32 2 T53 1 T56 1
valid_sources[0x3d] 9094 1 T28 3 T32 3 T54 1
valid_sources[0x3e] 9118 1 T20 5 T32 1 T42 8
valid_sources[0x3f] 8649 1 T32 1 T54 1 T56 2
valid_sources[0x40] 9225 1 T32 2 T42 1 T54 3
valid_sources[0x41] 10902 1 T32 2 T42 2 T54 2
valid_sources[0x42] 9234 1 T32 2 T42 2 T72 1
valid_sources[0x43] 10762 1 T20 6 T28 1 T42 5
valid_sources[0x44] 10491 1 T32 2 T42 1 T54 3
valid_sources[0x45] 8710 1 T32 1 T42 1 T54 1
valid_sources[0x46] 10219 1 T20 1 T58 2 T59 1
valid_sources[0x47] 9241 1 T32 1 T54 1 T58 3
valid_sources[0x48] 9486 1 T42 2 T58 1 T59 1
valid_sources[0x49] 10699 1 T32 2 T53 1 T54 1
valid_sources[0x4a] 8915 1 T32 2 T53 1 T54 1
valid_sources[0x4b] 10028 1 T20 2 T32 1 T53 2
valid_sources[0x4c] 11656 1 T32 2 T42 3 T44 3
valid_sources[0x4d] 9057 1 T32 1 T42 2 T58 1
valid_sources[0x4e] 10335 1 T58 4 T59 2 T118 4
valid_sources[0x4f] 9211 1 T20 14 T32 6 T55 1
valid_sources[0x50] 9613 1 T20 2 T32 1 T42 1
valid_sources[0x51] 11403 1 T32 2 T53 4 T54 1
valid_sources[0x52] 9830 1 T32 1 T42 1 T54 2
valid_sources[0x53] 10170 1 T54 3 T56 1 T58 1
valid_sources[0x54] 10702 1 T32 1 T53 2 T54 1
valid_sources[0x55] 9374 1 T20 11 T32 1 T118 4
valid_sources[0x56] 10730 1 T20 9 T32 4 T42 1
valid_sources[0x57] 10005 1 T32 6 T42 5 T54 1
valid_sources[0x58] 9377 1 T20 2 T32 3 T42 3
valid_sources[0x59] 9310 1 T32 3 T56 1 T59 2
valid_sources[0x5a] 10126 1 T32 1 T56 2 T58 2
valid_sources[0x5b] 9670 1 T32 5 T54 1 T56 2
valid_sources[0x5c] 11025 1 T20 15 T32 2 T42 2
valid_sources[0x5d] 11336 1 T32 2 T42 5 T54 3
valid_sources[0x5e] 9398 1 T28 2 T32 6 T42 3
valid_sources[0x5f] 9215 1 T32 1 T54 2 T56 3
valid_sources[0x60] 9269 1 T32 1 T42 1 T54 2
valid_sources[0x61] 10127 1 T32 3 T42 2 T53 1
valid_sources[0x62] 8955 1 T32 2 T53 10 T56 2
valid_sources[0x63] 10622 1 T32 2 T54 4 T56 4
valid_sources[0x64] 9903 1 T32 2 T42 1 T53 1
valid_sources[0x65] 9162 1 T32 3 T54 1 T56 7
valid_sources[0x66] 11683 1 T20 1 T32 1 T42 7
valid_sources[0x67] 9491 1 T32 4 T54 2 T56 3
valid_sources[0x68] 9112 1 T20 1 T32 2 T42 1
valid_sources[0x69] 9529 1 T54 3 T56 9 T58 2
valid_sources[0x6a] 10003 1 T32 2 T54 2 T56 1
valid_sources[0x6b] 10378 1 T28 3 T54 1 T56 3
valid_sources[0x6c] 11086 1 T20 9 T28 3 T32 1
valid_sources[0x6d] 8971 1 T20 3 T32 1 T53 2
valid_sources[0x6e] 9044 1 T20 9 T54 1 T56 7
valid_sources[0x6f] 9315 1 T32 3 T58 1 T59 3
valid_sources[0x70] 9153 1 T20 6 T32 2 T42 5
valid_sources[0x71] 8923 1 T32 3 T42 4 T54 1
valid_sources[0x72] 10697 1 T54 1 T56 1 T58 2
valid_sources[0x73] 9262 1 T32 2 T42 3 T54 2
valid_sources[0x74] 9206 1 T20 6 T32 4 T53 3
valid_sources[0x75] 8313 1 T32 2 T54 1 T56 1
valid_sources[0x76] 9401 1 T32 2 T42 1 T53 3
valid_sources[0x77] 8724 1 T20 2 T32 2 T42 2
valid_sources[0x78] 9471 1 T28 4 T32 3 T42 1
valid_sources[0x79] 8977 1 T20 2 T32 2 T53 6
valid_sources[0x7a] 9723 1 T32 2 T42 4 T54 3
valid_sources[0x7b] 10127 1 T32 2 T42 1 T53 5
valid_sources[0x7c] 10247 1 T32 1 T53 5 T54 1
valid_sources[0x7d] 11372 1 T33 1 T53 1 T54 1
valid_sources[0x7e] 10059 1 T42 1 T43 20 T54 2
valid_sources[0x7f] 9617 1 T32 2 T54 1 T56 1
valid_sources[0x80] 8636 1 T32 3 T54 3 T56 4



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 515748 1 T20 45 T28 40 T32 109
values[0x0] all_enables biggest_size 768371 1 T20 78 T32 155 T42 127
values[0x1] all_enables biggest_size 767820 1 T20 82 T32 153 T42 123

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%