SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
tl_intg_err_cgs_wrap[rom_ctrl_regs_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
tl_intg_err_cgs_wrap[rom_ctrl_rom_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 1 | 13 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 1 | 1 | 50.00 | 100 | 0 | 0 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 1 | 13 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 1 | 1 | 50.00 | 100 | 0 | 0 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
[auto[1]] | 0 | 0 | - | - | - | - | - | - | ||||
auto[0] | 6733914 | 0 | T20 | 705 | T28 | 406 | T29 | 20 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 6733721 | 1 | T20 | 705 | T28 | 406 | T29 | 20 | ||||
values[1] | 19 | 1 | T55 | 1 | T57 | 1 | T70 | 1 | ||||
values[2] | 5 | 1 | T33 | 1 | T105 | 2 | T106 | 1 | ||||
values[3] | 94 | 1 | T33 | 6 | T44 | 4 | T55 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 6733704 | 1 | T20 | 705 | T28 | 406 | T29 | 20 | ||||
values[1] | 24 | 1 | T33 | 1 | T44 | 1 | T55 | 1 | ||||
values[2] | 9 | 1 | T44 | 1 | T55 | 1 | T57 | 1 | ||||
values[3] | 109 | 1 | T33 | 3 | T44 | 7 | T55 | 5 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 6733614 | 1 | T20 | 705 | T28 | 406 | T29 | 20 | ||||
auto[TlIntgErrCmd] | 90 | 1 | T33 | 3 | T44 | 5 | T57 | 2 | ||||
auto[TlIntgErrData] | 107 | 1 | T44 | 6 | T55 | 5 | T57 | 6 | ||||
auto[TlIntgErrBoth] | 103 | 1 | T33 | 7 | T44 | 9 | T55 | 5 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
[auto[0]] | 0 | 0 | - | - | - | - | - | - | ||||
auto[1] | 8153947 | 0 | T20 | 672 | T28 | 40 | T32 | 1433 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 8153746 | 1 | T20 | 672 | T28 | 40 | T32 | 1433 | ||||
values[1] | 17 | 1 | T33 | 1 | T44 | 2 | T57 | 1 | ||||
values[2] | 4 | 1 | T107 | 1 | T108 | 2 | T109 | 1 | ||||
values[3] | 100 | 1 | T33 | 3 | T44 | 9 | T55 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 8153746 | 1 | T20 | 672 | T28 | 40 | T32 | 1433 | ||||
values[1] | 22 | 1 | T33 | 3 | T57 | 1 | T110 | 2 | ||||
values[2] | 7 | 1 | T33 | 1 | T44 | 1 | T111 | 1 | ||||
values[3] | 94 | 1 | T33 | 3 | T44 | 2 | T55 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 8153647 | 1 | T20 | 672 | T28 | 40 | T32 | 1433 | ||||
auto[TlIntgErrCmd] | 99 | 1 | T44 | 12 | T55 | 6 | T57 | 3 | ||||
auto[TlIntgErrData] | 99 | 1 | T33 | 6 | T44 | 3 | T55 | 1 | ||||
auto[TlIntgErrBoth] | 102 | 1 | T33 | 4 | T44 | 5 | T55 | 3 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |