Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

5696246

1

T20

424

T32

944

T33

8

full_word

2457701

1

T20

248

T28

40

T32

489

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	8153647	1			T20	672		T28	40		T32	1433
auto[TlIntgErrCmd]	99	1			T44	12		T55	6		T57	3
auto[TlIntgErrData]	99	1			T33	6		T44	3		T55	1
auto[TlIntgErrBoth]	102	1			T33	4		T44	5		T55	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

977500

1

T20

96

T28

40

T32

228

auto[1]

7176447

1

T20

576

T32

1205

T33

3

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	412084	1			T20	46		T32	103		T42	33
auto[TlIntgErrNone]	partial	auto[1]	5283886	1			T20	378		T32	841		T42	785
auto[TlIntgErrNone]	full_word	auto[0]	565295	1			T20	50		T28	40		T32	125
auto[TlIntgErrNone]	full_word	auto[1]	1892382	1			T20	198		T32	364		T42	302
auto[TlIntgErrCmd]	partial	auto[0]	36	1			T44	4		T55	1		T57	2
auto[TlIntgErrCmd]	partial	auto[1]	54	1			T44	6		T55	5		T57	1
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T44	2		T71	1		T112	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T107	1		T113	1		T114	1
auto[TlIntgErrData]	partial	auto[0]	40	1			T33	3		T44	1		T57	3
auto[TlIntgErrData]	partial	auto[1]	50	1			T33	2		T44	2		T55	1
auto[TlIntgErrData]	full_word	auto[0]	6	1			T33	1		T57	1		T111	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T111	1		T112	1		T106	1
auto[TlIntgErrBoth]	partial	auto[0]	31	1			T33	2		T44	1		T55	1
auto[TlIntgErrBoth]	partial	auto[1]	65	1			T33	1		T44	4		T55	2
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T33	1		T70	1		T115	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T115	1		T109	1		T116	1