SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
rom_ctrl_kmac_cg | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 7 | 0 | 7 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_kmac_done | 3 | 0 | 3 | 100.00 | 100 | 1 | 1 | 0 | |
cp_kmac_ready | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 3 | 0 | 3 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
kmac_first | 498 | 1 | T28 | 21 | T31 | 1 | T36 | 2 | ||||
same_cycle | 22 | 1 | T67 | 1 | T8 | 1 | T14 | 1 | ||||
rom_first | 1542 | 1 | T20 | 1 | T29 | 1 | T30 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
stall_repeat | 100444944 | 1 | T20 | 67904 | T29 | 50075 | T30 | 67036 | ||||
stall_long | 10641218 | 1 | T20 | 7077 | T29 | 5623 | T30 | 6991 | ||||
stall_1 | 704189 | 1 | T20 | 208 | T29 | 491 | T30 | 212 | ||||
zero_delay_5 | 3262550 | 1 | T28 | 171780 | T31 | 8180 | T33 | 1 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |