ROM_CTRL Simulation Results

Sunday October 01 2023 19:02:47 UTC

GitHub Revision: `7b89440c3`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 3649974514

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	40.560s	16.472ms	50	50	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	16.190s	1.558ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	16.300s	2.129ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	12.760s	1.415ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	15.780s	1.984ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	16.520s	2.072ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	16.300s	2.129ms	20	20	100.00
		rom_ctrl_csr_aliasing	15.780s	1.984ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	14.480s	1.752ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	16.970s	41.124ms	5	5	100.00
V1		TOTAL			115	115	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	17.700s	8.932ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	2.196m	13.251ms	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	35.030s	19.346ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	16.800s	2.202ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	20.450s	2.043ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	20.450s	2.043ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	16.190s	1.558ms	5	5	100.00
		rom_ctrl_csr_rw	16.300s	2.129ms	20	20	100.00
		rom_ctrl_csr_aliasing	15.780s	1.984ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	17.060s	7.999ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	16.190s	1.558ms	5	5	100.00
		rom_ctrl_csr_rw	16.300s	2.129ms	20	20	100.00
		rom_ctrl_csr_aliasing	15.780s	1.984ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	17.060s	7.999ms	20	20	100.00
V2		TOTAL			240	240	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	11.897m	68.627ms	49	50	98.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	5.705m	40.432ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	1.954m	23.640ms	5	5	100.00
		rom_ctrl_tl_intg_err	1.438m	26.857ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	1.954m	23.640ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	11.897m	68.627ms	49	50	98.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	11.897m	68.627ms	49	50	98.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	11.897m	68.627ms	49	50	98.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	11.897m	68.627ms	49	50	98.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	11.897m	68.627ms	49	50	98.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	1.954m	23.640ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	1.954m	23.640ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	40.560s	16.472ms	50	50	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	40.560s	16.472ms	50	50	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	40.560s	16.472ms	50	50	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.438m	26.857ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	11.897m	68.627ms	49	50	98.00
		rom_ctrl_kmac_err_chk	35.030s	19.346ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	11.897m	68.627ms	49	50	98.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	11.897m	68.627ms	49	50	98.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	11.897m	68.627ms	49	50	98.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	5.705m	40.432ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	1.954m	23.640ms	5	5	100.00
V2S		TOTAL			94	95	98.95
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.713h	60.106ms	35	50	70.00
V3		TOTAL			35	50	70.00
		TOTAL			484	500	96.80

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	6	100.00
V2S	4	4	3	75.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.67	97.11	93.12	97.88	100.00	98.69	98.04	98.84

Failure Buckets

Job rom_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 11 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 11 failures.
  - 11.rom_ctrl_stress_all_with_rand_reset.1543355253
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/11.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:6c22fad3-a124-45f3-a33c-2cfc6c525948
```
  - 18.rom_ctrl_stress_all_with_rand_reset.1060799858
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/18.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:23e34c10-b5e2-45cd-a0b4-8a15548f85d3
```
  - ... and 9 more failures.

UVM_FATAL (cip_base_vseq.sv:245) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 3 failures:

Test rom_ctrl_stress_all_with_rand_reset has 3 failures.

23.rom_ctrl_stress_all_with_rand_reset.29144663
Line 225, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/23.rom_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 20743890237 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x7395332f
  UVM_INFO @ 20743890237 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

33.rom_ctrl_stress_all_with_rand_reset.2852566080
Line 212, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/33.rom_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 12010708317 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x5d858207
  UVM_INFO @ 12010708317 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR (rom_ctrl_scoreboard.sv:253) [scoreboard] Check failed pwrmgr_complete == *'b* (* [*] vs * [*]) pwrmgr signals never checked has 2 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 1 failures.
  - 14.rom_ctrl_stress_all_with_rand_reset.2383677830
    Line 430, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/14.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 438213451513 ps: (rom_ctrl_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
  UVM_INFO @ 438213451513 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_ctrl_corrupt_sig_fatal_chk has 1 failures.
  - 48.rom_ctrl_corrupt_sig_fatal_chk.4050590515
    Line 252, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/48.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log
```
  UVM_ERROR @ 32009137439 ps: (rom_ctrl_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
  UVM_INFO @ 32009137439 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```