Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_rom_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0



Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_rom_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_rom_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_rom_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_rom_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 208726 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 2163812 1 T24 172 T32 349 T34 29



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 590623 1 T24 67 T32 129 T34 6
values[0x0] 824801 1 T24 85 T32 188 T34 15
values[0x1] 957114 1 T24 100 T32 172 T34 17



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 92695 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 2279843 1 T24 203 T32 397 T34 31



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 9403 1 T40 6 T78 2 T50 2
valid_sources[0x01] 8803 1 T32 3 T39 1 T40 5
valid_sources[0x02] 9062 1 T24 1 T32 1 T39 3
valid_sources[0x03] 9703 1 T32 1 T39 1 T40 1
valid_sources[0x04] 9638 1 T24 1 T32 1 T40 9
valid_sources[0x05] 9482 1 T24 1 T32 1 T39 1
valid_sources[0x06] 10106 1 T24 1 T32 2 T34 1
valid_sources[0x07] 8993 1 T32 1 T40 3 T78 1
valid_sources[0x08] 9161 1 T24 3 T32 2 T38 8
valid_sources[0x09] 8789 1 T39 1 T40 2 T50 1
valid_sources[0x0a] 9453 1 T24 1 T34 1 T40 3
valid_sources[0x0b] 9604 1 T32 3 T39 1 T50 3
valid_sources[0x0c] 8631 1 T24 1 T32 4 T39 1
valid_sources[0x0d] 8878 1 T24 1 T32 1 T39 1
valid_sources[0x0e] 9733 1 T39 1 T47 2 T72 4
valid_sources[0x0f] 9640 1 T32 3 T37 10 T40 1
valid_sources[0x10] 9214 1 T24 1 T32 2 T39 1
valid_sources[0x11] 9383 1 T24 3 T32 3 T40 4
valid_sources[0x12] 9380 1 T24 1 T50 2 T47 1
valid_sources[0x13] 7817 1 T32 1 T50 1 T47 5
valid_sources[0x14] 9810 1 T32 2 T34 1 T39 1
valid_sources[0x15] 9617 1 T24 3 T32 4 T39 2
valid_sources[0x16] 9626 1 T24 3 T32 1 T40 1
valid_sources[0x17] 9884 1 T32 5 T40 6 T78 1
valid_sources[0x18] 9077 1 T24 2 T32 1 T46 1
valid_sources[0x19] 9456 1 T24 1 T32 1 T47 5
valid_sources[0x1a] 9300 1 T24 1 T32 1 T39 2
valid_sources[0x1b] 10294 1 T39 4 T40 1 T46 3
valid_sources[0x1c] 10062 1 T24 3 T32 1 T50 2
valid_sources[0x1d] 9289 1 T32 1 T39 6 T40 3
valid_sources[0x1e] 9816 1 T24 1 T45 2 T46 1
valid_sources[0x1f] 9589 1 T32 5 T34 1 T39 1
valid_sources[0x20] 9985 1 T24 1 T32 1 T39 5
valid_sources[0x21] 8804 1 T24 2 T38 9 T47 3
valid_sources[0x22] 9730 1 T32 2 T38 16 T78 2
valid_sources[0x23] 9123 1 T32 5 T40 17 T78 2
valid_sources[0x24] 8855 1 T24 2 T32 4 T46 4
valid_sources[0x25] 9556 1 T24 1 T32 1 T39 1
valid_sources[0x26] 9501 1 T24 1 T32 5 T40 7
valid_sources[0x27] 9853 1 T24 4 T32 1 T40 2
valid_sources[0x28] 8548 1 T39 1 T40 11 T46 10
valid_sources[0x29] 8499 1 T39 1 T50 1 T47 4
valid_sources[0x2a] 8661 1 T24 5 T32 1 T39 2
valid_sources[0x2b] 9377 1 T24 2 T32 3 T39 1
valid_sources[0x2c] 9615 1 T24 4 T32 2 T39 3
valid_sources[0x2d] 9093 1 T24 1 T32 1 T39 1
valid_sources[0x2e] 10127 1 T24 3 T32 3 T39 2
valid_sources[0x2f] 8694 1 T24 1 T47 2 T48 1
valid_sources[0x30] 8965 1 T24 1 T32 1 T40 5
valid_sources[0x31] 9136 1 T24 1 T32 1 T39 2
valid_sources[0x32] 9222 1 T24 1 T32 2 T34 1
valid_sources[0x33] 8095 1 T32 3 T40 1 T50 3
valid_sources[0x34] 9685 1 T32 3 T39 1 T78 1
valid_sources[0x35] 9401 1 T32 2 T39 3 T68 10
valid_sources[0x36] 8912 1 T46 1 T50 1 T47 3
valid_sources[0x37] 9250 1 T24 1 T32 2 T40 1
valid_sources[0x38] 8559 1 T32 2 T40 2 T78 1
valid_sources[0x39] 9281 1 T24 2 T32 1 T34 1
valid_sources[0x3a] 9293 1 T39 1 T78 1 T47 1
valid_sources[0x3b] 8979 1 T32 2 T34 2 T39 1
valid_sources[0x3c] 9024 1 T24 1 T32 2 T39 1
valid_sources[0x3d] 9801 1 T38 4 T39 1 T45 23
valid_sources[0x3e] 9169 1 T24 2 T32 1 T39 1
valid_sources[0x3f] 8996 1 T39 4 T46 4 T78 2
valid_sources[0x40] 9144 1 T24 4 T39 2 T78 1
valid_sources[0x41] 8767 1 T32 7 T39 1 T45 3
valid_sources[0x42] 9878 1 T24 2 T32 2 T40 4
valid_sources[0x43] 8570 1 T32 2 T39 3 T78 2
valid_sources[0x44] 8495 1 T24 1 T32 2 T40 3
valid_sources[0x45] 9064 1 T32 8 T40 6 T45 3
valid_sources[0x46] 9376 1 T24 1 T32 1 T39 1
valid_sources[0x47] 9382 1 T32 2 T40 2 T45 14
valid_sources[0x48] 8574 1 T24 3 T32 3 T40 1
valid_sources[0x49] 9298 1 T24 1 T39 1 T40 1
valid_sources[0x4a] 9513 1 T32 4 T40 4 T69 2
valid_sources[0x4b] 9471 1 T24 1 T32 1 T38 7
valid_sources[0x4c] 8802 1 T32 1 T39 1 T40 9
valid_sources[0x4d] 8853 1 T32 3 T39 4 T40 3
valid_sources[0x4e] 9375 1 T24 1 T39 1 T40 5
valid_sources[0x4f] 9579 1 T24 1 T32 1 T39 1
valid_sources[0x50] 10125 1 T24 1 T32 1 T34 2
valid_sources[0x51] 10114 1 T40 3 T45 2 T50 2
valid_sources[0x52] 8819 1 T39 3 T50 3 T75 1
valid_sources[0x53] 8945 1 T24 1 T32 2 T34 2
valid_sources[0x54] 8744 1 T24 1 T32 1 T39 1
valid_sources[0x55] 9025 1 T24 1 T32 1 T40 5
valid_sources[0x56] 8571 1 T32 6 T39 3 T40 4
valid_sources[0x57] 9182 1 T24 1 T78 1 T50 1
valid_sources[0x58] 9187 1 T24 2 T32 3 T34 2
valid_sources[0x59] 8917 1 T24 1 T40 11 T50 5
valid_sources[0x5a] 9664 1 T32 3 T78 1 T50 2
valid_sources[0x5b] 8286 1 T24 1 T32 2 T39 3
valid_sources[0x5c] 10385 1 T24 2 T39 3 T40 5
valid_sources[0x5d] 9489 1 T24 1 T38 1 T45 2
valid_sources[0x5e] 8591 1 T32 1 T39 1 T40 3
valid_sources[0x5f] 9282 1 T32 3 T78 1 T47 1
valid_sources[0x60] 8998 1 T40 4 T78 1 T50 1
valid_sources[0x61] 9942 1 T24 4 T32 2 T39 1
valid_sources[0x62] 9663 1 T39 4 T40 5 T50 1
valid_sources[0x63] 9772 1 T39 2 T50 1 T47 1
valid_sources[0x64] 10156 1 T32 1 T34 2 T47 4
valid_sources[0x65] 9313 1 T24 3 T32 2 T39 2
valid_sources[0x66] 8896 1 T24 1 T32 1 T47 2
valid_sources[0x67] 9400 1 T24 1 T39 1 T40 1
valid_sources[0x68] 9704 1 T39 1 T50 1 T47 5
valid_sources[0x69] 10008 1 T24 2 T32 1 T39 2
valid_sources[0x6a] 9377 1 T24 1 T32 1 T50 2
valid_sources[0x6b] 9393 1 T24 2 T32 4 T38 4
valid_sources[0x6c] 9503 1 T24 1 T32 5 T39 1
valid_sources[0x6d] 9097 1 T32 5 T39 2 T46 1
valid_sources[0x6e] 8731 1 T24 1 T32 1 T40 1
valid_sources[0x6f] 9133 1 T32 2 T50 5 T48 2
valid_sources[0x70] 8888 1 T24 2 T32 3 T40 2
valid_sources[0x71] 8721 1 T24 1 T32 1 T47 2
valid_sources[0x72] 9426 1 T24 2 T32 3 T50 1
valid_sources[0x73] 8538 1 T24 2 T32 3 T39 2
valid_sources[0x74] 8909 1 T24 1 T32 3 T38 1
valid_sources[0x75] 9437 1 T32 2 T45 20 T50 3
valid_sources[0x76] 9247 1 T32 4 T50 1 T47 1
valid_sources[0x77] 9076 1 T24 1 T32 3 T39 1
valid_sources[0x78] 9764 1 T32 2 T39 1 T40 1
valid_sources[0x79] 10125 1 T32 1 T40 4 T78 1
valid_sources[0x7a] 8266 1 T24 1 T32 2 T34 3
valid_sources[0x7b] 8215 1 T24 5 T32 1 T39 2
valid_sources[0x7c] 8611 1 T24 2 T32 2 T39 1
valid_sources[0x7d] 8608 1 T32 1 T38 18 T47 2
valid_sources[0x7e] 10010 1 T32 1 T78 1 T50 1
valid_sources[0x7f] 8134 1 T32 2 T46 4 T78 2
valid_sources[0x80] 8940 1 T24 1 T32 2 T38 2



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 546705 1 T24 4 T32 15 T36 1
values[0x0] all_enables biggest_size 808147 1 T24 74 T32 176 T34 15
values[0x1] all_enables biggest_size 808960 1 T24 94 T32 158 T34 14


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 481147 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 2130544 1 T32 2 T39 79 T45 2



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 583857 1 T24 4 T32 7 T39 17
values[0x0] 838529 1 T24 1 T32 7 T39 33
values[0x1] 1189305 1 T24 1 T32 3 T39 51



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 182520 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 2429171 1 T24 2 T32 10 T39 91



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 9841 1 T50 5 T72 2 T116 3
valid_sources[0x01] 12324 1 T39 1 T50 1 T116 2
valid_sources[0x02] 10477 1 T74 1 T73 2 T85 1
valid_sources[0x03] 11352 1 T50 2 T72 2 T85 1
valid_sources[0x04] 9269 1 T39 2 T50 4 T73 1
valid_sources[0x05] 11178 1 T39 1 T50 3 T74 1
valid_sources[0x06] 11990 1 T24 1 T48 1 T74 4
valid_sources[0x07] 10580 1 T39 1 T50 4 T74 1
valid_sources[0x08] 10760 1 T39 1 T50 1 T72 1
valid_sources[0x09] 10598 1 T46 2 T50 3 T117 1
valid_sources[0x0a] 9987 1 T50 3 T69 2 T72 2
valid_sources[0x0b] 10957 1 T50 5 T69 7 T72 3
valid_sources[0x0c] 10172 1 T39 1 T46 1 T50 5
valid_sources[0x0d] 8990 1 T39 1 T50 1 T73 2
valid_sources[0x0e] 9453 1 T39 1 T72 3 T73 2
valid_sources[0x0f] 10037 1 T46 1 T50 4 T72 1
valid_sources[0x10] 9702 1 T50 2 T48 1 T72 4
valid_sources[0x11] 9676 1 T50 2 T72 4 T73 1
valid_sources[0x12] 9217 1 T50 3 T85 1 T118 1
valid_sources[0x13] 11027 1 T50 2 T72 1 T116 4
valid_sources[0x14] 10838 1 T46 1 T74 2 T72 4
valid_sources[0x15] 10094 1 T50 1 T72 2 T116 7
valid_sources[0x16] 9572 1 T39 1 T50 1 T72 1
valid_sources[0x17] 10399 1 T39 1 T50 2 T72 2
valid_sources[0x18] 9613 1 T50 1 T72 1 T73 2
valid_sources[0x19] 9705 1 T46 2 T50 3 T72 4
valid_sources[0x1a] 9979 1 T39 1 T46 1 T50 3
valid_sources[0x1b] 10700 1 T39 1 T50 7 T48 1
valid_sources[0x1c] 11721 1 T46 1 T50 5 T72 3
valid_sources[0x1d] 11063 1 T50 2 T72 1 T73 1
valid_sources[0x1e] 9010 1 T50 1 T72 1 T73 3
valid_sources[0x1f] 9913 1 T32 17 T50 2 T72 2
valid_sources[0x20] 12174 1 T50 1 T47 19 T72 1
valid_sources[0x21] 8542 1 T50 1 T70 11 T72 1
valid_sources[0x22] 9896 1 T39 1 T50 3 T72 2
valid_sources[0x23] 9207 1 T48 1 T73 4 T119 2
valid_sources[0x24] 10738 1 T50 1 T72 1 T85 1
valid_sources[0x25] 10729 1 T50 6 T72 2 T73 6
valid_sources[0x26] 10126 1 T39 2 T46 1 T50 3
valid_sources[0x27] 9715 1 T50 4 T73 1 T116 9
valid_sources[0x28] 8951 1 T50 3 T72 2 T49 1
valid_sources[0x29] 9783 1 T39 1 T50 2 T85 2
valid_sources[0x2a] 9915 1 T39 1 T50 3 T116 14
valid_sources[0x2b] 10121 1 T50 1 T72 4 T73 1
valid_sources[0x2c] 9960 1 T39 1 T50 5 T85 1
valid_sources[0x2d] 10177 1 T50 1 T48 2 T69 5
valid_sources[0x2e] 9762 1 T72 2 T73 3 T85 1
valid_sources[0x2f] 9975 1 T50 2 T72 2 T49 1
valid_sources[0x30] 9435 1 T50 3 T72 1 T73 1
valid_sources[0x31] 10830 1 T39 1 T50 2 T85 1
valid_sources[0x32] 9816 1 T50 3 T49 1 T85 1
valid_sources[0x33] 10027 1 T39 1 T50 2 T72 3
valid_sources[0x34] 9788 1 T50 5 T72 1 T73 5
valid_sources[0x35] 9798 1 T50 3 T48 1 T74 5
valid_sources[0x36] 9180 1 T46 1 T50 5 T72 1
valid_sources[0x37] 9922 1 T39 1 T50 2 T72 3
valid_sources[0x38] 10407 1 T48 1 T116 3 T119 1
valid_sources[0x39] 8787 1 T50 3 T72 1 T85 1
valid_sources[0x3a] 8545 1 T39 2 T50 2 T75 1
valid_sources[0x3b] 9336 1 T50 3 T48 1 T85 1
valid_sources[0x3c] 9395 1 T50 4 T72 6 T81 1
valid_sources[0x3d] 10022 1 T50 2 T69 1 T72 2
valid_sources[0x3e] 10031 1 T45 1 T50 3 T72 1
valid_sources[0x3f] 10031 1 T50 3 T69 1 T72 4
valid_sources[0x40] 9732 1 T46 1 T50 2 T70 7
valid_sources[0x41] 11623 1 T39 1 T50 1 T72 2
valid_sources[0x42] 9600 1 T50 3 T72 2 T73 2
valid_sources[0x43] 10204 1 T39 2 T85 1 T116 3
valid_sources[0x44] 11503 1 T50 5 T48 1 T73 6
valid_sources[0x45] 9508 1 T46 1 T72 1 T73 3
valid_sources[0x46] 12145 1 T39 2 T72 2 T73 3
valid_sources[0x47] 10499 1 T39 1 T46 1 T50 2
valid_sources[0x48] 9702 1 T39 1 T50 1 T72 2
valid_sources[0x49] 11144 1 T50 2 T72 1 T73 4
valid_sources[0x4a] 8920 1 T50 1 T72 2 T73 1
valid_sources[0x4b] 10838 1 T39 1 T50 4 T72 2
valid_sources[0x4c] 10984 1 T50 5 T48 2 T73 2
valid_sources[0x4d] 10643 1 T50 8 T69 3 T72 1
valid_sources[0x4e] 10197 1 T50 1 T47 15 T72 3
valid_sources[0x4f] 9701 1 T73 4 T116 1 T118 1
valid_sources[0x50] 9945 1 T39 2 T50 3 T73 2
valid_sources[0x51] 10716 1 T50 1 T69 1 T72 1
valid_sources[0x52] 10326 1 T39 1 T50 7 T48 1
valid_sources[0x53] 9570 1 T39 1 T50 3 T75 1
valid_sources[0x54] 9764 1 T50 2 T72 2 T73 1
valid_sources[0x55] 9319 1 T50 4 T72 3 T73 1
valid_sources[0x56] 9823 1 T39 1 T46 1 T50 7
valid_sources[0x57] 11043 1 T50 7 T71 1 T75 1
valid_sources[0x58] 9677 1 T39 2 T50 2 T72 1
valid_sources[0x59] 9415 1 T50 1 T72 2 T116 8
valid_sources[0x5a] 10942 1 T50 3 T48 1 T72 1
valid_sources[0x5b] 10498 1 T50 3 T69 1 T72 2
valid_sources[0x5c] 11532 1 T50 1 T72 4 T73 3
valid_sources[0x5d] 8890 1 T39 1 T46 1 T50 5
valid_sources[0x5e] 10262 1 T50 2 T73 6 T116 1
valid_sources[0x5f] 10747 1 T50 4 T69 2 T73 7
valid_sources[0x60] 9672 1 T46 1 T50 5 T69 6
valid_sources[0x61] 10444 1 T69 1 T73 4 T116 5
valid_sources[0x62] 8622 1 T45 1 T46 1 T50 7
valid_sources[0x63] 10693 1 T39 1 T72 3 T116 3
valid_sources[0x64] 9145 1 T39 1 T50 5 T48 1
valid_sources[0x65] 11259 1 T39 1 T50 1 T72 2
valid_sources[0x66] 10335 1 T50 4 T72 3 T73 6
valid_sources[0x67] 10287 1 T39 1 T50 3 T74 2
valid_sources[0x68] 9503 1 T50 1 T72 1 T85 1
valid_sources[0x69] 11210 1 T50 5 T72 1 T85 1
valid_sources[0x6a] 10063 1 T45 1 T50 1 T72 4
valid_sources[0x6b] 11283 1 T45 1 T50 2 T48 1
valid_sources[0x6c] 10995 1 T50 7 T69 1 T72 2
valid_sources[0x6d] 9460 1 T50 4 T72 1 T49 1
valid_sources[0x6e] 9576 1 T50 2 T69 1 T72 1
valid_sources[0x6f] 10107 1 T46 1 T50 1 T74 1
valid_sources[0x70] 10013 1 T50 7 T73 2 T85 2
valid_sources[0x71] 9923 1 T50 5 T72 2 T73 1
valid_sources[0x72] 8818 1 T50 4 T70 3 T72 1
valid_sources[0x73] 9941 1 T50 3 T72 1 T85 2
valid_sources[0x74] 10367 1 T39 1 T50 1 T74 1
valid_sources[0x75] 11061 1 T50 4 T72 1 T73 13
valid_sources[0x76] 10963 1 T50 3 T69 1 T72 2
valid_sources[0x77] 10510 1 T50 1 T116 2 T119 7
valid_sources[0x78] 11727 1 T46 1 T50 4 T48 2
valid_sources[0x79] 11118 1 T46 1 T50 1 T69 19
valid_sources[0x7a] 8660 1 T50 1 T72 1 T73 4
valid_sources[0x7b] 9668 1 T50 6 T72 3 T73 8
valid_sources[0x7c] 8925 1 T50 2 T85 1 T116 5
valid_sources[0x7d] 10031 1 T39 2 T46 1 T50 3
valid_sources[0x7e] 10772 1 T46 1 T50 2 T72 4
valid_sources[0x7f] 9965 1 T46 1 T50 2 T72 2
valid_sources[0x80] 10624 1 T50 5 T72 2 T85 1



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 536667 1 T32 1 T39 17 T45 2
values[0x0] all_enables biggest_size 797423 1 T32 1 T39 30 T46 18
values[0x1] all_enables biggest_size 796454 1 T39 32 T46 20 T50 206

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