Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

5906100

1

T24

10

T32

18

T39

221

full_word

2552274

1

T32

2

T39

90

T45

2

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	8458064	1			T39	311		T46	161		T50	1716
auto[TlIntgErrCmd]	104	1			T24	4		T32	7		T45	9
auto[TlIntgErrData]	101	1			T24	2		T32	10		T45	5
auto[TlIntgErrBoth]	105	1			T24	4		T32	3		T45	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1016568

1

T24

6

T32

8

T39

30

auto[1]

7441806

1

T24

4

T32

12

T39

281

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	428038	1			T39	11		T46	6		T50	54
auto[TlIntgErrNone]	partial	auto[1]	5477774	1			T39	210		T46	97		T50	970
auto[TlIntgErrNone]	full_word	auto[0]	588396	1			T39	19		T46	14		T50	172
auto[TlIntgErrNone]	full_word	auto[1]	1963856	1			T39	71		T46	44		T50	520
auto[TlIntgErrCmd]	partial	auto[0]	45	1			T24	2		T32	5		T45	3
auto[TlIntgErrCmd]	partial	auto[1]	50	1			T24	2		T32	2		T45	5
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T45	1		T110	1		T111	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T110	1		T107	2		T109	2
auto[TlIntgErrData]	partial	auto[0]	39	1			T24	1		T32	2		T45	4
auto[TlIntgErrData]	partial	auto[1]	54	1			T24	1		T32	7		T45	1
auto[TlIntgErrData]	full_word	auto[0]	4	1			T76	2		T112	1		T109	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T32	1		T110	1		T113	1
auto[TlIntgErrBoth]	partial	auto[0]	40	1			T24	3		T45	2		T68	1
auto[TlIntgErrBoth]	partial	auto[1]	60	1			T24	1		T32	2		T45	3
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T32	1		T45	1		T71	1
auto[TlIntgErrBoth]	full_word	auto[1]	2	1			T111	1		T114	1		-	-