SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.rom_ctrl_regs_csr_assert | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
94.98 | 100.00 | 98.28 | 97.33 | 100.00 | 79.31 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
TlulOOBAddrErr_A | 330103090 | 3855634 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 330103090 | 3855634 | 0 | 0 |
T24 | 13335 | 2 | 0 | 0 |
T32 | 24482 | 11 | 0 | 0 |
T33 | 57632 | 0 | 0 | 0 |
T34 | 197566 | 0 | 0 | 0 |
T35 | 61566 | 0 | 0 | 0 |
T36 | 8282 | 0 | 0 | 0 |
T37 | 20885 | 0 | 0 | 0 |
T38 | 81842 | 0 | 0 | 0 |
T39 | 58886 | 93 | 0 | 0 |
T40 | 8416 | 0 | 0 | 0 |
T45 | 0 | 9 | 0 | 0 |
T46 | 0 | 49 | 0 | 0 |
T50 | 0 | 581 | 0 | 0 |
T68 | 0 | 7 | 0 | 0 |
T69 | 0 | 339 | 0 | 0 |
T70 | 0 | 9 | 0 | 0 |
T71 | 0 | 3 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |