Line Coverage for Module :
rom_ctrl
| Line No. | Total | Covered | Percent |
TOTAL | | 65 | 65 | 100.00 |
CONT_ASSIGN | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 122 | 1 | 1 | 100.00 |
CONT_ASSIGN | 123 | 1 | 1 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
CONT_ASSIGN | 125 | 1 | 1 | 100.00 |
CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 222 | 1 | 1 | 100.00 |
CONT_ASSIGN | 268 | 1 | 1 | 100.00 |
CONT_ASSIGN | 323 | 1 | 1 | 100.00 |
CONT_ASSIGN | 425 | 1 | 1 | 100.00 |
CONT_ASSIGN | 425 | 1 | 1 | 100.00 |
CONT_ASSIGN | 425 | 1 | 1 | 100.00 |
CONT_ASSIGN | 425 | 1 | 1 | 100.00 |
CONT_ASSIGN | 425 | 1 | 1 | 100.00 |
CONT_ASSIGN | 425 | 1 | 1 | 100.00 |
CONT_ASSIGN | 425 | 1 | 1 | 100.00 |
CONT_ASSIGN | 425 | 1 | 1 | 100.00 |
CONT_ASSIGN | 426 | 1 | 1 | 100.00 |
CONT_ASSIGN | 426 | 1 | 1 | 100.00 |
CONT_ASSIGN | 426 | 1 | 1 | 100.00 |
CONT_ASSIGN | 426 | 1 | 1 | 100.00 |
CONT_ASSIGN | 426 | 1 | 1 | 100.00 |
CONT_ASSIGN | 426 | 1 | 1 | 100.00 |
CONT_ASSIGN | 426 | 1 | 1 | 100.00 |
CONT_ASSIGN | 426 | 1 | 1 | 100.00 |
CONT_ASSIGN | 428 | 1 | 1 | 100.00 |
CONT_ASSIGN | 428 | 1 | 1 | 100.00 |
CONT_ASSIGN | 428 | 1 | 1 | 100.00 |
CONT_ASSIGN | 428 | 1 | 1 | 100.00 |
CONT_ASSIGN | 428 | 1 | 1 | 100.00 |
CONT_ASSIGN | 428 | 1 | 1 | 100.00 |
CONT_ASSIGN | 428 | 1 | 1 | 100.00 |
CONT_ASSIGN | 428 | 1 | 1 | 100.00 |
CONT_ASSIGN | 429 | 1 | 1 | 100.00 |
CONT_ASSIGN | 429 | 1 | 1 | 100.00 |
CONT_ASSIGN | 429 | 1 | 1 | 100.00 |
CONT_ASSIGN | 429 | 1 | 1 | 100.00 |
CONT_ASSIGN | 429 | 1 | 1 | 100.00 |
CONT_ASSIGN | 429 | 1 | 1 | 100.00 |
CONT_ASSIGN | 429 | 1 | 1 | 100.00 |
CONT_ASSIGN | 429 | 1 | 1 | 100.00 |
CONT_ASSIGN | 431 | 1 | 1 | 100.00 |
CONT_ASSIGN | 431 | 1 | 1 | 100.00 |
CONT_ASSIGN | 431 | 1 | 1 | 100.00 |
CONT_ASSIGN | 431 | 1 | 1 | 100.00 |
CONT_ASSIGN | 431 | 1 | 1 | 100.00 |
CONT_ASSIGN | 431 | 1 | 1 | 100.00 |
CONT_ASSIGN | 431 | 1 | 1 | 100.00 |
CONT_ASSIGN | 431 | 1 | 1 | 100.00 |
CONT_ASSIGN | 432 | 1 | 1 | 100.00 |
CONT_ASSIGN | 432 | 1 | 1 | 100.00 |
CONT_ASSIGN | 432 | 1 | 1 | 100.00 |
CONT_ASSIGN | 432 | 1 | 1 | 100.00 |
CONT_ASSIGN | 432 | 1 | 1 | 100.00 |
CONT_ASSIGN | 432 | 1 | 1 | 100.00 |
CONT_ASSIGN | 432 | 1 | 1 | 100.00 |
CONT_ASSIGN | 432 | 1 | 1 | 100.00 |
CONT_ASSIGN | 436 | 1 | 1 | 100.00 |
CONT_ASSIGN | 438 | 1 | 1 | 100.00 |
CONT_ASSIGN | 441 | 1 | 1 | 100.00 |
CONT_ASSIGN | 442 | 1 | 1 | 100.00 |
CONT_ASSIGN | 443 | 1 | 1 | 100.00 |
CONT_ASSIGN | 444 | 1 | 1 | 100.00 |
CONT_ASSIGN | 449 | 1 | 1 | 100.00 |
CONT_ASSIGN | 453 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv' or '../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
117 |
1 |
1 |
122 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
128 |
1 |
1 |
222 |
1 |
1 |
268 |
1 |
1 |
323 |
1 |
1 |
425 |
8 |
8 |
426 |
8 |
8 |
428 |
8 |
8 |
429 |
8 |
8 |
431 |
8 |
8 |
432 |
8 |
8 |
436 |
1 |
1 |
438 |
1 |
1 |
441 |
1 |
1 |
442 |
1 |
1 |
443 |
1 |
1 |
444 |
1 |
1 |
449 |
1 |
1 |
453 |
1 |
1 |
Cond Coverage for Module :
rom_ctrl
| Total | Covered | Percent |
Conditions | 58 | 57 | 98.28 |
Logical | 58 | 57 | 98.28 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 222
EXPRESSION (tl_rom_h2d_upstream.a_valid ? tl_rom_h2d_upstream.a_address[2+:RomIndexWidth] : '0)
-------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T4,T5 |
LINE 268
EXPRESSION (bus_rom_rvalid_raw & ((!internal_alert)))
---------1-------- ---------2---------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T19,T20,T35 |
1 | 1 | Covered | T1,T4,T5 |
LINE 429
EXPRESSION (exp_digest_de && (0[2:0] == exp_digest_idx))
------1------ -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 429
SUB-EXPRESSION (0[2:0] == exp_digest_idx)
-------------1------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 429
EXPRESSION (exp_digest_de && (1[2:0] == exp_digest_idx))
------1------ -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 429
SUB-EXPRESSION (1[2:0] == exp_digest_idx)
-------------1------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 429
EXPRESSION (exp_digest_de && (2[2:0] == exp_digest_idx))
------1------ -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 429
SUB-EXPRESSION (2[2:0] == exp_digest_idx)
-------------1------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 429
EXPRESSION (exp_digest_de && (3[2:0] == exp_digest_idx))
------1------ -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 429
SUB-EXPRESSION (3[2:0] == exp_digest_idx)
-------------1------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 429
EXPRESSION (exp_digest_de && (4[2:0] == exp_digest_idx))
------1------ -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 429
SUB-EXPRESSION (4[2:0] == exp_digest_idx)
-------------1------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 429
EXPRESSION (exp_digest_de && (5[2:0] == exp_digest_idx))
------1------ -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 429
SUB-EXPRESSION (5[2:0] == exp_digest_idx)
-------------1------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 429
EXPRESSION (exp_digest_de && (6[2:0] == exp_digest_idx))
------1------ -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 429
SUB-EXPRESSION (6[2:0] == exp_digest_idx)
-------------1------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 429
EXPRESSION (exp_digest_de && (7[2:0] == exp_digest_idx))
------1------ -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 429
SUB-EXPRESSION (7[2:0] == exp_digest_idx)
-------------1------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 436
EXPRESSION (rom_reg_integrity_error | rom_integrity_error | reg_integrity_error)
-----------1----------- ---------2--------- ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 1 | Covered | T38,T39,T40 |
0 | 1 | 0 | Not Covered | |
1 | 0 | 0 | Unreachable | |
LINE 438
EXPRESSION (checker_alert | mux_alert)
------1------ ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T19,T20,T35 |
1 | 0 | Covered | T2,T6,T10 |
LINE 449
EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
---------1--------- ----------2---------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T41,T42 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T3,T41,T42 |
LINE 453
EXPRESSION (bus_integrity_error | checker_alert | mux_alert)
---------1--------- ------2------ ----3----
-1- | -2- | -3- | Status | Tests |
0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 1 | Covered | T19,T20,T35 |
0 | 1 | 0 | Covered | T2,T6,T10 |
1 | 0 | 0 | Covered | T38,T39,T40 |
Toggle Coverage for Module :
rom_ctrl
| Total | Covered | Percent |
Totals |
61 |
56 |
91.80 |
Total Bits |
2882 |
2805 |
97.33 |
Total Bits 0->1 |
1441 |
1402 |
97.29 |
Total Bits 1->0 |
1441 |
1403 |
97.36 |
| | | |
Ports |
61 |
56 |
91.80 |
Port Bits |
2882 |
2805 |
97.33 |
Port Bits 0->1 |
1441 |
1402 |
97.29 |
Port Bits 1->0 |
1441 |
1403 |
97.36 |
Port Details
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i |
Yes |
Yes |
T22,T23,T24 |
Yes |
T22,T23,T24 |
INPUT |
rst_ni |
Yes |
Yes |
T23,T24,T25 |
Yes |
T22,T23,T24 |
INPUT |
rom_cfg_i.cfg[3:0] |
No |
No |
|
No |
|
INPUT |
rom_cfg_i.cfg_en |
No |
No |
|
No |
|
INPUT |
rom_tl_i.d_ready |
Yes |
Yes |
T22,T23,T24 |
Yes |
T22,T23,T24 |
INPUT |
rom_tl_i.a_user.data_intg[6:0] |
Yes |
Yes |
T23,T24,T25 |
Yes |
T23,T24,T25 |
INPUT |
rom_tl_i.a_user.cmd_intg[6:0] |
Yes |
Yes |
T24,T25,T26 |
Yes |
T23,T24,T25 |
INPUT |
rom_tl_i.a_user.instr_type[3:0] |
Yes |
Yes |
T23,T29,T31 |
Yes |
T23,T28,T29 |
INPUT |
rom_tl_i.a_user.rsvd[4:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
rom_tl_i.a_data[31:0] |
Yes |
Yes |
T23,T24,T25 |
Yes |
T24,T25,T26 |
INPUT |
rom_tl_i.a_mask[3:0] |
Yes |
Yes |
T26,T29,T30 |
Yes |
T23,T26,T29 |
INPUT |
rom_tl_i.a_address[31:0] |
Yes |
Yes |
T26,T29,T30 |
Yes |
T23,T26,T29 |
INPUT |
rom_tl_i.a_source[7:0] |
Yes |
Yes |
T24,T25,T29 |
Yes |
T24,T25,T29 |
INPUT |
rom_tl_i.a_size[1:0] |
Yes |
Yes |
T26,T29,T31 |
Yes |
T23,T26,T29 |
INPUT |
rom_tl_i.a_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
rom_tl_i.a_opcode[2:0] |
Yes |
Yes |
T23,T28,T29 |
Yes |
T26,T29,T31 |
INPUT |
rom_tl_i.a_valid |
Yes |
Yes |
T24,T25,T26 |
Yes |
T24,T25,T26 |
INPUT |
rom_tl_o.a_ready |
Yes |
Yes |
T23,T24,T25 |
Yes |
T22,T23,T24 |
OUTPUT |
rom_tl_o.d_error |
Yes |
Yes |
T26,T29,T31 |
Yes |
T26,T29,T31 |
OUTPUT |
rom_tl_o.d_user.data_intg[6:0] |
Yes |
Yes |
T24,T25,T43 |
Yes |
T24,T25,T43 |
OUTPUT |
rom_tl_o.d_user.rsp_intg[5:0] |
Yes |
Yes |
*T24,*T25,T26 |
Yes |
T24,T25,T26 |
OUTPUT |
rom_tl_o.d_user.rsp_intg[6] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
rom_tl_o.d_data[31:0] |
Yes |
Yes |
T24,T25,T31 |
Yes |
T24,T25,T31 |
OUTPUT |
rom_tl_o.d_sink |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
rom_tl_o.d_source[7:0] |
Yes |
Yes |
T24,T25,T26 |
Yes |
T24,T25,T26 |
OUTPUT |
rom_tl_o.d_size[1:0] |
Yes |
Yes |
T26,T29,T31 |
Yes |
T26,T29,T31 |
OUTPUT |
rom_tl_o.d_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
rom_tl_o.d_opcode[0] |
Yes |
Yes |
*T26,*T29,*T31 |
Yes |
T26,T29,T31 |
OUTPUT |
rom_tl_o.d_opcode[2:1] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
rom_tl_o.d_valid |
Yes |
Yes |
T24,T25,T26 |
Yes |
T24,T25,T26 |
OUTPUT |
regs_tl_i.d_ready |
Yes |
Yes |
T22,T23,T24 |
Yes |
T22,T23,T24 |
INPUT |
regs_tl_i.a_user.data_intg[6:0] |
Yes |
Yes |
T22,T23,T24 |
Yes |
T22,T23,T24 |
INPUT |
regs_tl_i.a_user.cmd_intg[6:0] |
Yes |
Yes |
T22,T23,T24 |
Yes |
T22,T23,T24 |
INPUT |
regs_tl_i.a_user.instr_type[3:0] |
Yes |
Yes |
T25,T26,T29 |
Yes |
T25,T26,T29 |
INPUT |
regs_tl_i.a_user.rsvd[4:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
regs_tl_i.a_data[31:0] |
Yes |
Yes |
T22,T23,T24 |
Yes |
T22,T23,T24 |
INPUT |
regs_tl_i.a_mask[3:0] |
Yes |
Yes |
T22,T24,T25 |
Yes |
T22,T24,T25 |
INPUT |
regs_tl_i.a_address[31:0] |
Yes |
Yes |
T22,T24,T25 |
Yes |
T22,T24,T25 |
INPUT |
regs_tl_i.a_source[7:0] |
Yes |
Yes |
T22,T23,T24 |
Yes |
T22,T23,T24 |
INPUT |
regs_tl_i.a_size[1:0] |
Yes |
Yes |
T22,T23,T24 |
Yes |
T22,T23,T24 |
INPUT |
regs_tl_i.a_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
regs_tl_i.a_opcode[2:0] |
Yes |
Yes |
T22,T23,T24 |
Yes |
T22,T23,T24 |
INPUT |
regs_tl_i.a_valid |
Yes |
Yes |
T22,T23,T24 |
Yes |
T22,T23,T24 |
INPUT |
regs_tl_o.a_ready |
Yes |
Yes |
T22,T23,T24 |
Yes |
T22,T23,T24 |
OUTPUT |
regs_tl_o.d_error |
Yes |
Yes |
T26,T29,T31 |
Yes |
T26,T29,T31 |
OUTPUT |
regs_tl_o.d_user.data_intg[6:0] |
Yes |
Yes |
T1,T2,T6 |
Yes |
T1,T2,T6 |
OUTPUT |
regs_tl_o.d_user.rsp_intg[5:0] |
Yes |
Yes |
*T22,*T23,*T24 |
Yes |
T22,T23,T24 |
OUTPUT |
regs_tl_o.d_user.rsp_intg[6] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
regs_tl_o.d_data[31:0] |
Yes |
Yes |
T22,T23,T24 |
Yes |
T22,T23,T24 |
OUTPUT |
regs_tl_o.d_sink |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
regs_tl_o.d_source[7:0] |
Yes |
Yes |
T22,T23,T24 |
Yes |
T22,T23,T24 |
OUTPUT |
regs_tl_o.d_size[1:0] |
Yes |
Yes |
T22,T23,T24 |
Yes |
T22,T23,T24 |
OUTPUT |
regs_tl_o.d_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
regs_tl_o.d_opcode[0] |
Yes |
Yes |
*T22,*T24,*T25 |
Yes |
T22,T23,T24 |
OUTPUT |
regs_tl_o.d_opcode[2:1] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
regs_tl_o.d_valid |
Yes |
Yes |
T22,T23,T24 |
Yes |
T22,T23,T24 |
OUTPUT |
alert_rx_i[0].ack_n |
Yes |
Yes |
T22,T23,T24 |
Yes |
T22,T23,T24 |
INPUT |
alert_rx_i[0].ack_p |
Yes |
Yes |
T22,T23,T24 |
Yes |
T22,T23,T24 |
INPUT |
alert_rx_i[0].ping_n |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
alert_rx_i[0].ping_p |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
alert_tx_o[0].alert_n |
Yes |
Yes |
T22,T23,T24 |
Yes |
T22,T23,T24 |
OUTPUT |
alert_tx_o[0].alert_p |
Yes |
Yes |
T22,T23,T24 |
Yes |
T22,T23,T24 |
OUTPUT |
pwrmgr_data_o.good[3:0] |
Yes |
Yes |
T22,T23,T24 |
Yes |
T22,T23,T24 |
OUTPUT |
pwrmgr_data_o.done[3:0] |
Yes |
Yes |
T22,T23,T24 |
Yes |
T24,T25,T43 |
OUTPUT |
keymgr_data_o.valid |
Yes |
Yes |
T24,T25,T43 |
Yes |
T22,T23,T24 |
OUTPUT |
keymgr_data_o.data[255:0] |
Yes |
Yes |
T24,T25,T43 |
Yes |
T22,T23,T24 |
OUTPUT |
kmac_data_i.error |
No |
Yes |
T2,T6,T10 |
No |
|
INPUT |
kmac_data_i.digest_share1[383:0] |
Yes |
Yes |
T24,T25,T43 |
Yes |
T24,T25,T43 |
INPUT |
kmac_data_i.digest_share0[383:0] |
Yes |
Yes |
T24,T25,T43 |
Yes |
T24,T25,T43 |
INPUT |
kmac_data_i.done |
Yes |
Yes |
T22,T23,T24 |
Yes |
T22,T23,T24 |
INPUT |
kmac_data_i.ready |
Yes |
Yes |
T22,T23,T24 |
Yes |
T22,T23,T24 |
INPUT |
kmac_data_o.last |
Yes |
Yes |
T22,T23,T24 |
Yes |
T22,T23,T24 |
OUTPUT |
kmac_data_o.strb[7:0] |
No |
No |
|
No |
|
OUTPUT |
kmac_data_o.data[38:0] |
Yes |
Yes |
T22,T23,T24 |
Yes |
T22,T23,T24 |
OUTPUT |
kmac_data_o.data[63:39] |
No |
No |
|
No |
|
OUTPUT |
kmac_data_o.valid |
Yes |
Yes |
T22,T23,T24 |
Yes |
T22,T23,T24 |
OUTPUT |
*Tests covering at least one bit in the range
Branch Coverage for Module :
rom_ctrl
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
TERNARY |
222 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv' or '../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 222 (tl_rom_h2d_upstream.a_valid) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
rom_ctrl
Assertion Details
AlertTxOKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
239648369 |
239459890 |
0 |
0 |
T1 |
378267 |
378118 |
0 |
0 |
T2 |
270838 |
270675 |
0 |
0 |
T3 |
53948 |
53895 |
0 |
0 |
T4 |
283757 |
283654 |
0 |
0 |
T5 |
128419 |
127880 |
0 |
0 |
T6 |
123362 |
123192 |
0 |
0 |
T7 |
311866 |
311744 |
0 |
0 |
T8 |
157388 |
157203 |
0 |
0 |
T9 |
9625 |
9557 |
0 |
0 |
T10 |
157311 |
157193 |
0 |
0 |
BusRomIndicesMatch_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
239633803 |
239452042 |
0 |
0 |
T1 |
378267 |
378118 |
0 |
0 |
T2 |
270838 |
270675 |
0 |
0 |
T3 |
53948 |
53895 |
0 |
0 |
T4 |
283757 |
283654 |
0 |
0 |
T5 |
128419 |
127880 |
0 |
0 |
T6 |
123362 |
123192 |
0 |
0 |
T7 |
311866 |
311744 |
0 |
0 |
T8 |
157388 |
157203 |
0 |
0 |
T9 |
9625 |
9557 |
0 |
0 |
T10 |
157311 |
157193 |
0 |
0 |
FpvSecCmFifoRptrCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
239648369 |
0 |
0 |
0 |
FpvSecCmFifoWptrCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
239648369 |
0 |
0 |
0 |
FpvSecCmRegWeOnehotCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
239648369 |
80 |
0 |
0 |
T38 |
18918 |
20 |
0 |
0 |
T39 |
63334 |
20 |
0 |
0 |
T40 |
0 |
10 |
0 |
0 |
T44 |
0 |
20 |
0 |
0 |
T45 |
0 |
10 |
0 |
0 |
T46 |
136258 |
0 |
0 |
0 |
T47 |
29844 |
0 |
0 |
0 |
T48 |
279773 |
0 |
0 |
0 |
T49 |
139804 |
0 |
0 |
0 |
T50 |
321876 |
0 |
0 |
0 |
T51 |
29534 |
0 |
0 |
0 |
T52 |
329594 |
0 |
0 |
0 |
T53 |
189225 |
0 |
0 |
0 |
KeymgrDataODataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
239648369 |
79394692 |
0 |
0 |
T1 |
378267 |
1756 |
0 |
0 |
T2 |
270838 |
64 |
0 |
0 |
T3 |
53948 |
281 |
0 |
0 |
T4 |
283757 |
1632 |
0 |
0 |
T5 |
128419 |
4282 |
0 |
0 |
T6 |
123362 |
287 |
0 |
0 |
T7 |
311866 |
1442 |
0 |
0 |
T8 |
157388 |
1334 |
0 |
0 |
T9 |
9625 |
1352 |
0 |
0 |
T10 |
157311 |
64 |
0 |
0 |
KeymgrDataODataKnown_AKnownEnable
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
239648369 |
239459890 |
0 |
0 |
T1 |
378267 |
378118 |
0 |
0 |
T2 |
270838 |
270675 |
0 |
0 |
T3 |
53948 |
53895 |
0 |
0 |
T4 |
283757 |
283654 |
0 |
0 |
T5 |
128419 |
127880 |
0 |
0 |
T6 |
123362 |
123192 |
0 |
0 |
T7 |
311866 |
311744 |
0 |
0 |
T8 |
157388 |
157203 |
0 |
0 |
T9 |
9625 |
9557 |
0 |
0 |
T10 |
157311 |
157193 |
0 |
0 |
KeymgrDataOValidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
239648369 |
239459890 |
0 |
0 |
T1 |
378267 |
378118 |
0 |
0 |
T2 |
270838 |
270675 |
0 |
0 |
T3 |
53948 |
53895 |
0 |
0 |
T4 |
283757 |
283654 |
0 |
0 |
T5 |
128419 |
127880 |
0 |
0 |
T6 |
123362 |
123192 |
0 |
0 |
T7 |
311866 |
311744 |
0 |
0 |
T8 |
157388 |
157203 |
0 |
0 |
T9 |
9625 |
9557 |
0 |
0 |
T10 |
157311 |
157193 |
0 |
0 |
KeymgrValidChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
239648369 |
0 |
0 |
338 |
KmacDataODataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
239648369 |
159925941 |
0 |
0 |
T1 |
378267 |
376160 |
0 |
0 |
T2 |
270838 |
270455 |
0 |
0 |
T3 |
53948 |
53592 |
0 |
0 |
T4 |
283757 |
281967 |
0 |
0 |
T5 |
128419 |
123279 |
0 |
0 |
T6 |
123362 |
122674 |
0 |
0 |
T7 |
311866 |
310222 |
0 |
0 |
T8 |
157388 |
155696 |
0 |
0 |
T9 |
9625 |
8184 |
0 |
0 |
T10 |
157311 |
156920 |
0 |
0 |
KmacDataODataKnown_AKnownEnable
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
239648369 |
239459890 |
0 |
0 |
T1 |
378267 |
378118 |
0 |
0 |
T2 |
270838 |
270675 |
0 |
0 |
T3 |
53948 |
53895 |
0 |
0 |
T4 |
283757 |
283654 |
0 |
0 |
T5 |
128419 |
127880 |
0 |
0 |
T6 |
123362 |
123192 |
0 |
0 |
T7 |
311866 |
311744 |
0 |
0 |
T8 |
157388 |
157203 |
0 |
0 |
T9 |
9625 |
9557 |
0 |
0 |
T10 |
157311 |
157193 |
0 |
0 |
KmacDataOValidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
239648369 |
239459890 |
0 |
0 |
T1 |
378267 |
378118 |
0 |
0 |
T2 |
270838 |
270675 |
0 |
0 |
T3 |
53948 |
53895 |
0 |
0 |
T4 |
283757 |
283654 |
0 |
0 |
T5 |
128419 |
127880 |
0 |
0 |
T6 |
123362 |
123192 |
0 |
0 |
T7 |
311866 |
311744 |
0 |
0 |
T8 |
157388 |
157203 |
0 |
0 |
T9 |
9625 |
9557 |
0 |
0 |
T10 |
157311 |
157193 |
0 |
0 |
PwrmgrDataChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
239648369 |
0 |
0 |
338 |
PwrmgrDataOKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
239648369 |
239459890 |
0 |
0 |
T1 |
378267 |
378118 |
0 |
0 |
T2 |
270838 |
270675 |
0 |
0 |
T3 |
53948 |
53895 |
0 |
0 |
T4 |
283757 |
283654 |
0 |
0 |
T5 |
128419 |
127880 |
0 |
0 |
T6 |
123362 |
123192 |
0 |
0 |
T7 |
311866 |
311744 |
0 |
0 |
T8 |
157388 |
157203 |
0 |
0 |
T9 |
9625 |
9557 |
0 |
0 |
T10 |
157311 |
157193 |
0 |
0 |
RegsTlOAReadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
239648369 |
239459890 |
0 |
0 |
T1 |
378267 |
378118 |
0 |
0 |
T2 |
270838 |
270675 |
0 |
0 |
T3 |
53948 |
53895 |
0 |
0 |
T4 |
283757 |
283654 |
0 |
0 |
T5 |
128419 |
127880 |
0 |
0 |
T6 |
123362 |
123192 |
0 |
0 |
T7 |
311866 |
311744 |
0 |
0 |
T8 |
157388 |
157203 |
0 |
0 |
T9 |
9625 |
9557 |
0 |
0 |
T10 |
157311 |
157193 |
0 |
0 |
RegsTlODDataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
239648369 |
11833522 |
0 |
0 |
T1 |
378267 |
130 |
0 |
0 |
T2 |
270838 |
1 |
0 |
0 |
T3 |
53948 |
13 |
0 |
0 |
T4 |
283757 |
135 |
0 |
0 |
T5 |
128419 |
435 |
0 |
0 |
T6 |
123362 |
1 |
0 |
0 |
T7 |
311866 |
32 |
0 |
0 |
T8 |
157388 |
32 |
0 |
0 |
T9 |
9625 |
0 |
0 |
0 |
T10 |
157311 |
5 |
0 |
0 |
T41 |
0 |
4 |
0 |
0 |
RegsTlODDataKnown_AKnownEnable
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
239648369 |
239459890 |
0 |
0 |
T1 |
378267 |
378118 |
0 |
0 |
T2 |
270838 |
270675 |
0 |
0 |
T3 |
53948 |
53895 |
0 |
0 |
T4 |
283757 |
283654 |
0 |
0 |
T5 |
128419 |
127880 |
0 |
0 |
T6 |
123362 |
123192 |
0 |
0 |
T7 |
311866 |
311744 |
0 |
0 |
T8 |
157388 |
157203 |
0 |
0 |
T9 |
9625 |
9557 |
0 |
0 |
T10 |
157311 |
157193 |
0 |
0 |
RegsTlODValidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
239648369 |
239459890 |
0 |
0 |
T1 |
378267 |
378118 |
0 |
0 |
T2 |
270838 |
270675 |
0 |
0 |
T3 |
53948 |
53895 |
0 |
0 |
T4 |
283757 |
283654 |
0 |
0 |
T5 |
128419 |
127880 |
0 |
0 |
T6 |
123362 |
123192 |
0 |
0 |
T7 |
311866 |
311744 |
0 |
0 |
T8 |
157388 |
157203 |
0 |
0 |
T9 |
9625 |
9557 |
0 |
0 |
T10 |
157311 |
157193 |
0 |
0 |
RomTlOAReadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
239648369 |
239459890 |
0 |
0 |
T1 |
378267 |
378118 |
0 |
0 |
T2 |
270838 |
270675 |
0 |
0 |
T3 |
53948 |
53895 |
0 |
0 |
T4 |
283757 |
283654 |
0 |
0 |
T5 |
128419 |
127880 |
0 |
0 |
T6 |
123362 |
123192 |
0 |
0 |
T7 |
311866 |
311744 |
0 |
0 |
T8 |
157388 |
157203 |
0 |
0 |
T9 |
9625 |
9557 |
0 |
0 |
T10 |
157311 |
157193 |
0 |
0 |
RomTlODDataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
239648369 |
14698375 |
0 |
0 |
T1 |
378267 |
78 |
0 |
0 |
T2 |
270838 |
0 |
0 |
0 |
T3 |
53948 |
0 |
0 |
0 |
T4 |
283757 |
407 |
0 |
0 |
T5 |
128419 |
601 |
0 |
0 |
T6 |
123362 |
0 |
0 |
0 |
T7 |
311866 |
77 |
0 |
0 |
T8 |
157388 |
291 |
0 |
0 |
T9 |
9625 |
349 |
0 |
0 |
T10 |
157311 |
0 |
0 |
0 |
T11 |
0 |
287 |
0 |
0 |
T19 |
0 |
12 |
0 |
0 |
T20 |
0 |
34 |
0 |
0 |
T21 |
0 |
272 |
0 |
0 |
RomTlODDataKnown_AKnownEnable
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
239648369 |
239459890 |
0 |
0 |
T1 |
378267 |
378118 |
0 |
0 |
T2 |
270838 |
270675 |
0 |
0 |
T3 |
53948 |
53895 |
0 |
0 |
T4 |
283757 |
283654 |
0 |
0 |
T5 |
128419 |
127880 |
0 |
0 |
T6 |
123362 |
123192 |
0 |
0 |
T7 |
311866 |
311744 |
0 |
0 |
T8 |
157388 |
157203 |
0 |
0 |
T9 |
9625 |
9557 |
0 |
0 |
T10 |
157311 |
157193 |
0 |
0 |
RomTlODValidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
239648369 |
239459890 |
0 |
0 |
T1 |
378267 |
378118 |
0 |
0 |
T2 |
270838 |
270675 |
0 |
0 |
T3 |
53948 |
53895 |
0 |
0 |
T4 |
283757 |
283654 |
0 |
0 |
T5 |
128419 |
127880 |
0 |
0 |
T6 |
123362 |
123192 |
0 |
0 |
T7 |
311866 |
311744 |
0 |
0 |
T8 |
157388 |
157203 |
0 |
0 |
T9 |
9625 |
9557 |
0 |
0 |
T10 |
157311 |
157193 |
0 |
0 |
StabilityChkKmac_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
239648369 |
159923252 |
0 |
0 |
T1 |
378267 |
376158 |
0 |
0 |
T2 |
270838 |
270453 |
0 |
0 |
T3 |
53948 |
53591 |
0 |
0 |
T4 |
283757 |
281965 |
0 |
0 |
T5 |
128419 |
123272 |
0 |
0 |
T6 |
123362 |
122672 |
0 |
0 |
T7 |
311866 |
310220 |
0 |
0 |
T8 |
157388 |
155694 |
0 |
0 |
T9 |
9625 |
8183 |
0 |
0 |
T10 |
157311 |
156918 |
0 |
0 |
StabilityChkkeymgr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
239648369 |
79393358 |
0 |
0 |
T1 |
378267 |
1754 |
0 |
0 |
T2 |
270838 |
63 |
0 |
0 |
T3 |
53948 |
280 |
0 |
0 |
T4 |
283757 |
1630 |
0 |
0 |
T5 |
128419 |
4277 |
0 |
0 |
T6 |
123362 |
286 |
0 |
0 |
T7 |
311866 |
1440 |
0 |
0 |
T8 |
157388 |
1332 |
0 |
0 |
T9 |
9625 |
1351 |
0 |
0 |
T10 |
157311 |
63 |
0 |
0 |
TlAccessChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
239648369 |
160065198 |
0 |
0 |
T1 |
378267 |
376362 |
0 |
0 |
T2 |
270838 |
270611 |
0 |
0 |
T3 |
53948 |
53614 |
0 |
0 |
T4 |
283757 |
282022 |
0 |
0 |
T5 |
128419 |
123598 |
0 |
0 |
T6 |
123362 |
122905 |
0 |
0 |
T7 |
311866 |
310302 |
0 |
0 |
T8 |
157388 |
155869 |
0 |
0 |
T9 |
9625 |
8205 |
0 |
0 |
T10 |
157311 |
157129 |
0 |
0 |
gen_asserts_with_scrambling.FpvSecCmCheckerFsmAlert_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
239648369 |
80 |
0 |
0 |
T38 |
18918 |
20 |
0 |
0 |
T39 |
63334 |
20 |
0 |
0 |
T40 |
0 |
10 |
0 |
0 |
T44 |
0 |
20 |
0 |
0 |
T45 |
0 |
10 |
0 |
0 |
T46 |
136258 |
0 |
0 |
0 |
T47 |
29844 |
0 |
0 |
0 |
T48 |
279773 |
0 |
0 |
0 |
T49 |
139804 |
0 |
0 |
0 |
T50 |
321876 |
0 |
0 |
0 |
T51 |
29534 |
0 |
0 |
0 |
T52 |
329594 |
0 |
0 |
0 |
T53 |
189225 |
0 |
0 |
0 |
gen_asserts_with_scrambling.FpvSecCmCompareAddrCtrCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
239648369 |
0 |
0 |
0 |
gen_asserts_with_scrambling.FpvSecCmCompareFsmAlert_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
239648369 |
581 |
0 |
0 |
T12 |
189148 |
0 |
0 |
0 |
T20 |
120223 |
11 |
0 |
0 |
T21 |
9457 |
0 |
0 |
0 |
T35 |
305485 |
4 |
0 |
0 |
T36 |
453540 |
20 |
0 |
0 |
T54 |
0 |
5 |
0 |
0 |
T55 |
0 |
10 |
0 |
0 |
T56 |
0 |
20 |
0 |
0 |
T57 |
0 |
20 |
0 |
0 |
T58 |
0 |
5 |
0 |
0 |
T59 |
0 |
10 |
0 |
0 |
T60 |
0 |
5 |
0 |
0 |
T61 |
676248 |
0 |
0 |
0 |
T62 |
87604 |
0 |
0 |
0 |
T63 |
45285 |
0 |
0 |
0 |
T64 |
66132 |
0 |
0 |
0 |
T65 |
8307 |
0 |
0 |
0 |
gen_fsm_scramble_enabled_asserts.BusLocalEscChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
239648369 |
0 |
0 |
0 |