SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.rom_ctrl_regs_csr_assert | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
94.98 | 100.00 | 98.28 | 97.33 | 100.00 | 79.31 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
TlulOOBAddrErr_A | 277209489 | 2761352 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 277209489 | 2761352 | 0 | 0 |
T26 | 200458 | 2 | 0 | 0 |
T27 | 148630 | 0 | 0 | 0 |
T28 | 41123 | 0 | 0 | 0 |
T29 | 96977 | 2 | 0 | 0 |
T30 | 74516 | 0 | 0 | 0 |
T31 | 153057 | 4 | 0 | 0 |
T43 | 113282 | 0 | 0 | 0 |
T66 | 21866 | 135 | 0 | 0 |
T67 | 0 | 17 | 0 | 0 |
T68 | 0 | 13 | 0 | 0 |
T69 | 0 | 5 | 0 | 0 |
T70 | 0 | 64 | 0 | 0 |
T71 | 0 | 6 | 0 | 0 |
T72 | 0 | 5 | 0 | 0 |
T73 | 204153 | 0 | 0 | 0 |
T74 | 8298 | 0 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |