Group : tb.dut.u_rom_ctrl_cov_if::rom_ctrl_tlul_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tb.dut.u_rom_ctrl_cov_if::rom_ctrl_tlul_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
62.50 62.50 1 100 1 1 64 64


Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_rom_ctrl_cov_0/rom_ctrl_cov_if.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
rom_ctrl_tlul_cg 62.50 1 100 1 64 64




Group Instance : rom_ctrl_tlul_cg
Comment: TLUL interface behaviors
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
62.50 1 100 1 64 64




Summary for Group Instance rom_ctrl_tlul_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 3 5 62.50


Variables for Group Instance rom_ctrl_tlul_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regs_req_check 3 2 1 33.33 100 1 1 0
cp_rom_invalid_condition 2 1 1 50.00 100 1 1 0
cp_rom_req_check 3 0 3 100.00 100 1 1 0


Summary for Variable cp_regs_req_check

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 2 1 33.33


User Defined Bins for cp_regs_req_check

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
req_and_done 0 1 1
req_before_done 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
req_after_done 3300 1 T3 32 T4 2 T5 32



Summary for Variable cp_rom_invalid_condition

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 1 1 50.00


User Defined Bins for cp_rom_invalid_condition

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
check_invalid 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
check_valid 278705890 1 T17 131208 T18 131683 T19 146006



Summary for Variable cp_rom_req_check

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rom_req_check

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
req_after_done 5780 1 T30 29 T31 29 T32 29
req_and_done 50 1 T12 1 T89 1 T92 1
req_before_done 320 1 T30 11 T31 11 T32 11

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%