Group : cip_base_pkg::tl_intg_err_cg_wrap::tl_intg_err_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : cip_base_pkg::tl_intg_err_cg_wrap::tl_intg_err_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
85.71 79.17 1 100 1 1 64 64


Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_intg_err_cgs_wrap[rom_ctrl_rom_reg_block] 75.00 1 100 1 64 64
tl_intg_err_cgs_wrap[rom_ctrl_regs_reg_block] 83.33 1 100 1 64 64




Group Instance : tl_intg_err_cgs_wrap[rom_ctrl_rom_reg_block]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
75.00 1 100 1 64 64




Summary for Group Instance tl_intg_err_cgs_wrap[rom_ctrl_rom_reg_block]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 14 4 10 75.00


Variables for Group Instance tl_intg_err_cgs_wrap[rom_ctrl_rom_reg_block]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_is_mem 2 1 1 50.00 100 0 0 2
cp_num_cmd_err_bits 4 1 3 75.00 100 1 1 0
cp_num_data_err_bits 4 2 2 50.00 100 1 1 0
cp_tl_intg_err_type 4 0 4 100.00 100 1 1 0



Group Instance : tl_intg_err_cgs_wrap[rom_ctrl_regs_reg_block]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
83.33 1 100 1 64 64




Summary for Group Instance tl_intg_err_cgs_wrap[rom_ctrl_regs_reg_block]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 14 3 11 83.33


Variables for Group Instance tl_intg_err_cgs_wrap[rom_ctrl_regs_reg_block]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_is_mem 2 1 1 50.00 100 0 0 2
cp_num_cmd_err_bits 4 1 3 75.00 100 1 1 0
cp_num_data_err_bits 4 1 3 75.00 100 1 1 0
cp_tl_intg_err_type 4 0 4 100.00 100 1 1 0


Summary for Variable cp_is_mem

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_is_mem

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
[auto[0]] 0 0 - - - - - -
auto[1] 56760 0 T17 1814 T18 44 T19 20



Summary for Variable cp_num_cmd_err_bits

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 1 3 75.00


User Defined Bins for cp_num_cmd_err_bits

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
values[2] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0] 56520 1 T17 1814 T18 44 T19 8
values[1] 80 1 T19 4 T49 4 T50 4
values[3] 120 1 T19 6 T49 6 T50 6



Summary for Variable cp_num_data_err_bits

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 2 2 50.00


User Defined Bins for cp_num_data_err_bits

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
values[1] 0 1 1
values[2] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0] 56480 1 T17 1814 T18 44 T19 6
values[3] 100 1 T19 5 T49 5 T50 5



Summary for Variable cp_tl_intg_err_type

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 4 0 4 100.00


Automatically Generated Bins for cp_tl_intg_err_type

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] 56360 1 T17 1814 T18 44 T22 1814
auto[TlIntgErrCmd] 120 1 T19 6 T49 6 T50 6
auto[TlIntgErrData] 160 1 T19 8 T49 8 T50 8
auto[TlIntgErrBoth] 120 1 T19 6 T49 6 T50 6


Summary for Variable cp_is_mem

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_is_mem

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
[auto[1]] 0 0 - - - - - -
auto[0] 59585 0 T17 1320 T18 49 T19 501



Summary for Variable cp_num_cmd_err_bits

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 1 3 75.00


User Defined Bins for cp_num_cmd_err_bits

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
values[2] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0] 59325 1 T17 1320 T18 49 T19 488
values[1] 40 1 T19 2 T49 2 T50 2
values[3] 140 1 T19 7 T49 7 T50 7



Summary for Variable cp_num_data_err_bits

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 1 3 75.00


User Defined Bins for cp_num_data_err_bits

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
values[2] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0] 59265 1 T17 1320 T18 49 T19 485
values[1] 40 1 T19 2 T49 2 T50 2
values[3] 140 1 T19 7 T49 7 T50 7



Summary for Variable cp_tl_intg_err_type

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 4 0 4 100.00


Automatically Generated Bins for cp_tl_intg_err_type

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] 59185 1 T17 1320 T18 49 T19 481
auto[TlIntgErrCmd] 80 1 T19 4 T49 4 T50 4
auto[TlIntgErrData] 140 1 T19 7 T49 7 T50 7
auto[TlIntgErrBoth] 180 1 T19 9 T49 9 T50 9

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