Group : tb.dut.u_rom_ctrl_cov_if::rom_ctrl_kmac_cg
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Group : tb.dut.u_rom_ctrl_cov_if::rom_ctrl_kmac_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
85.71 85.71 1 100 1 1 64 64


Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_rom_ctrl_cov_0/rom_ctrl_cov_if.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
rom_ctrl_kmac_cg 85.71 1 100 1 64 64




Group Instance : rom_ctrl_kmac_cg
Comment: KMAC interface behaviors
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
85.71 1 100 1 64 64




Summary for Group Instance rom_ctrl_kmac_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 7 1 6 85.71


Variables for Group Instance rom_ctrl_kmac_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_kmac_done 3 0 3 100.00 100 1 1 0
cp_kmac_ready 4 1 3 75.00 100 1 1 0


Summary for Variable cp_kmac_done

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_kmac_done

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
kmac_first 70 1 T30 1 T31 1 T32 1
same_cycle 70 1 T30 1 T31 1 T32 1
rom_first 1810 1 T17 1 T18 1 T19 1



Summary for Variable cp_kmac_ready

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 1 3 75.00


User Defined Bins for cp_kmac_ready

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
zero_delay_5 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
stall_repeat 138036960 1 T17 65386 T18 65606 T19 70960
stall_long 14542325 1 T17 6862 T18 6885 T19 7455
stall_1 546220 1 T17 253 T18 252 T19 277

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%