Unified Coverage Report :: Module :: prim_secded_inv_39_32_dec

Module : prim_secded_inv_39_32_dec

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_39_32_dec.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_tl_adapter_rom.gen_cmd_intg_check.u_cmd_intg_chk.u_tlul_data_integ_dec.u_data_chk	98.75			98.75
tb.dut.u_reg_regs.u_chk.u_tlul_data_integ_dec.u_data_chk	100.00			100.00

---

Module Instance : tb.dut.u_tl_adapter_rom.gen_cmd_intg_check.u_cmd_intg_chk.u_tlul_data_integ_dec.u_data_chk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.75			98.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.75			98.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_tlul_data_integ_dec

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_regs.u_chk.u_tlul_data_integ_dec.u_data_chk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_tlul_data_integ_dec

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : prim_secded_inv_39_32_dec

	Total	Covered	Percent
Totals	4	4	100.00
Total Bits	160	160	100.00
Total Bits 0->1	80	80	100.00
Total Bits 1->0	80	80	100.00

Ports	4	4	100.00
Port Bits	160	160	100.00
Port Bits 0->1	80	80	100.00
Port Bits 1->0	80	80	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[38:0]	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
data_o[31:0]	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	OUTPUT
syndrome_o[6:0]	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	OUTPUT
err_o[1:0]	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	OUTPUT

Toggle Coverage for Instance : tb.dut.u_tl_adapter_rom.gen_cmd_intg_check.u_cmd_intg_chk.u_tlul_data_integ_dec.u_data_chk

	Total	Covered	Percent
Totals	4	3	75.00
Total Bits	160	158	98.75
Total Bits 0->1	80	79	98.75
Total Bits 1->0	80	79	98.75

Ports	4	3	75.00
Port Bits	160	158	98.75
Port Bits 0->1	80	79	98.75
Port Bits 1->0	80	79	98.75

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[38:0]	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
data_o[31:0]	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	OUTPUT
syndrome_o[6:0]	Yes	Yes	T19,T49,T50	Yes	T19,T49,T50	OUTPUT
err_o[0]	Yes	Yes	*T19,*T49,*T50	Yes	T19,T49,T50	OUTPUT
err_o[1]	No	No		No		OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.u_reg_regs.u_chk.u_tlul_data_integ_dec.u_data_chk

	Total	Covered	Percent
Totals	4	4	100.00
Total Bits	160	160	100.00
Total Bits 0->1	80	80	100.00
Total Bits 1->0	80	80	100.00

Ports	4	4	100.00
Port Bits	160	160	100.00
Port Bits 0->1	80	80	100.00
Port Bits 1->0	80	80	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[38:0]	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
data_o[31:0]	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	OUTPUT
syndrome_o[6:0]	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	OUTPUT
err_o[1:0]	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	OUTPUT