Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : rom_ctrl
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.98 100.00 98.28 97.33 100.00 79.31

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut 94.98 100.00 98.28 97.33 100.00 79.31



Module Instance : tb.dut

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.98 100.00 98.28 97.33 100.00 79.31


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.35 97.11 92.68 97.88 100.00 98.37 98.04


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
tb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_alert_tx[0].u_alert_sender 100.00 100.00
gen_fsm_scramble_enabled.u_checker_fsm 95.92 100.00 96.30 90.00 100.00 98.31 90.91
gen_rom_scramble_enabled.u_rom 98.21 92.86 100.00 100.00 100.00
regs_tlul_assert_device 100.00 100.00 100.00 100.00
rom_ctrl_regs_csr_assert 100.00 100.00
rom_tlul_assert_device 99.30 100.00 100.00 97.90
u_mux 95.24 100.00 85.71 100.00
u_reg_regs 99.72 99.41 99.21 100.00 100.00 100.00
u_rom_top 100.00 100.00 100.00 100.00
u_tl_adapter_rom 93.77 91.56 83.06 99.07 95.18 100.00
u_tl_rom_h2d_buf 100.00 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : rom_ctrl
Line No.TotalCoveredPercent
TOTAL6565100.00
CONT_ASSIGN11711100.00
CONT_ASSIGN12211100.00
CONT_ASSIGN12311100.00
CONT_ASSIGN12411100.00
CONT_ASSIGN12511100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN22211100.00
CONT_ASSIGN26811100.00
CONT_ASSIGN32311100.00
CONT_ASSIGN42511100.00
CONT_ASSIGN42511100.00
CONT_ASSIGN42511100.00
CONT_ASSIGN42511100.00
CONT_ASSIGN42511100.00
CONT_ASSIGN42511100.00
CONT_ASSIGN42511100.00
CONT_ASSIGN42511100.00
CONT_ASSIGN42611100.00
CONT_ASSIGN42611100.00
CONT_ASSIGN42611100.00
CONT_ASSIGN42611100.00
CONT_ASSIGN42611100.00
CONT_ASSIGN42611100.00
CONT_ASSIGN42611100.00
CONT_ASSIGN42611100.00
CONT_ASSIGN42811100.00
CONT_ASSIGN42811100.00
CONT_ASSIGN42811100.00
CONT_ASSIGN42811100.00
CONT_ASSIGN42811100.00
CONT_ASSIGN42811100.00
CONT_ASSIGN42811100.00
CONT_ASSIGN42811100.00
CONT_ASSIGN42911100.00
CONT_ASSIGN42911100.00
CONT_ASSIGN42911100.00
CONT_ASSIGN42911100.00
CONT_ASSIGN42911100.00
CONT_ASSIGN42911100.00
CONT_ASSIGN42911100.00
CONT_ASSIGN42911100.00
CONT_ASSIGN43111100.00
CONT_ASSIGN43111100.00
CONT_ASSIGN43111100.00
CONT_ASSIGN43111100.00
CONT_ASSIGN43111100.00
CONT_ASSIGN43111100.00
CONT_ASSIGN43111100.00
CONT_ASSIGN43111100.00
CONT_ASSIGN43211100.00
CONT_ASSIGN43211100.00
CONT_ASSIGN43211100.00
CONT_ASSIGN43211100.00
CONT_ASSIGN43211100.00
CONT_ASSIGN43211100.00
CONT_ASSIGN43211100.00
CONT_ASSIGN43211100.00
CONT_ASSIGN43611100.00
CONT_ASSIGN43811100.00
CONT_ASSIGN44111100.00
CONT_ASSIGN44211100.00
CONT_ASSIGN44311100.00
CONT_ASSIGN44411100.00
CONT_ASSIGN44911100.00
CONT_ASSIGN45311100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv' or '../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
117 1 1
122 1 1
123 1 1
124 1 1
125 1 1
128 1 1
222 1 1
268 1 1
323 1 1
425 8 8
426 8 8
428 8 8
429 8 8
431 8 8
432 8 8
436 1 1
438 1 1
441 1 1
442 1 1
443 1 1
444 1 1
449 1 1
453 1 1


Cond Coverage for Module : rom_ctrl
TotalCoveredPercent
Conditions585798.28
Logical585798.28
Non-Logical00
Event00

 LINE       222
 EXPRESSION (tl_rom_h2d_upstream.a_valid ? tl_rom_h2d_upstream.a_address[2+:RomIndexWidth] : '0)
             -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T4

 LINE       268
 EXPRESSION (bus_rom_rvalid_raw & ((!internal_alert)))
             ---------1--------   ---------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T4,T18
11CoveredT1,T2,T4

 LINE       429
 EXPRESSION (exp_digest_de && (0[2:0] == exp_digest_idx))
             ------1------    -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       429
 SUB-EXPRESSION (0[2:0] == exp_digest_idx)
                -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       429
 EXPRESSION (exp_digest_de && (1[2:0] == exp_digest_idx))
             ------1------    -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       429
 SUB-EXPRESSION (1[2:0] == exp_digest_idx)
                -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       429
 EXPRESSION (exp_digest_de && (2[2:0] == exp_digest_idx))
             ------1------    -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       429
 SUB-EXPRESSION (2[2:0] == exp_digest_idx)
                -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       429
 EXPRESSION (exp_digest_de && (3[2:0] == exp_digest_idx))
             ------1------    -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       429
 SUB-EXPRESSION (3[2:0] == exp_digest_idx)
                -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       429
 EXPRESSION (exp_digest_de && (4[2:0] == exp_digest_idx))
             ------1------    -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       429
 SUB-EXPRESSION (4[2:0] == exp_digest_idx)
                -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       429
 EXPRESSION (exp_digest_de && (5[2:0] == exp_digest_idx))
             ------1------    -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       429
 SUB-EXPRESSION (5[2:0] == exp_digest_idx)
                -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       429
 EXPRESSION (exp_digest_de && (6[2:0] == exp_digest_idx))
             ------1------    -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       429
 SUB-EXPRESSION (6[2:0] == exp_digest_idx)
                -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       429
 EXPRESSION (exp_digest_de && (7[2:0] == exp_digest_idx))
             ------1------    -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       429
 SUB-EXPRESSION (7[2:0] == exp_digest_idx)
                -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       436
 EXPRESSION (rom_reg_integrity_error | rom_integrity_error | reg_integrity_error)
             -----------1-----------   ---------2---------   ---------3---------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT6,T29,T30
010Not Covered
100Unreachable

 LINE       438
 EXPRESSION (checker_alert | mux_alert)
             ------1------   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T4,T18
10CoveredT1,T3,T4

 LINE       449
 EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
             ---------1---------   ----------2---------
-1--2-StatusTests
01CoveredT5,T8,T31
10CoveredT1,T2,T3
11CoveredT5,T8,T31

 LINE       453
 EXPRESSION (bus_integrity_error | checker_alert | mux_alert)
             ---------1---------   ------2------   ----3----
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT1,T4,T18
010CoveredT1,T3,T4
100CoveredT6,T29,T30

Toggle Coverage for Module : rom_ctrl
TotalCoveredPercent
Totals 61 56 91.80
Total Bits 2882 2805 97.33
Total Bits 0->1 1441 1402 97.29
Total Bits 1->0 1441 1403 97.36

Ports 61 56 91.80
Port Bits 2882 2805 97.33
Port Bits 0->1 1441 1402 97.29
Port Bits 1->0 1441 1403 97.36

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rom_cfg_i.cfg[3:0] No No No INPUT
rom_cfg_i.cfg_en No No No INPUT
rom_tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rom_tl_i.a_user.data_intg[6:0] Yes Yes T2,T4,T7 Yes T2,T4,T5 INPUT
rom_tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T4 Yes T1,T2,T4 INPUT
rom_tl_i.a_user.instr_type[3:0] Yes Yes T4,T9,T11 Yes T4,T9,T11 INPUT
rom_tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
rom_tl_i.a_data[31:0] Yes Yes T2,T4,T7 Yes T2,T4,T5 INPUT
rom_tl_i.a_mask[3:0] Yes Yes T2,T4,T7 Yes T2,T4,T7 INPUT
rom_tl_i.a_address[31:0] Yes Yes T2,T4,T7 Yes T2,T4,T7 INPUT
rom_tl_i.a_source[7:0] Yes Yes T2,T4,T5 Yes T2,T4,T7 INPUT
rom_tl_i.a_size[1:0] Yes Yes T2,T4,T7 Yes T2,T4,T7 INPUT
rom_tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
rom_tl_i.a_opcode[2:0] Yes Yes T4,T9,T11 Yes T4,T5,T9 INPUT
rom_tl_i.a_valid Yes Yes T1,T2,T4 Yes T1,T2,T4 INPUT
rom_tl_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
rom_tl_o.d_error Yes Yes T13,T14,T15 Yes T13,T14,T15 OUTPUT
rom_tl_o.d_user.data_intg[6:0] Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
rom_tl_o.d_user.rsp_intg[5:0] Yes Yes *T1,*T2,*T4 Yes T1,T2,T4 OUTPUT
rom_tl_o.d_user.rsp_intg[6] Unreachable Unreachable Unreachable OUTPUT
rom_tl_o.d_data[31:0] Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
rom_tl_o.d_sink Unreachable Unreachable Unreachable OUTPUT
rom_tl_o.d_source[7:0] Yes Yes T2,T4,T7 Yes T2,T4,T7 OUTPUT
rom_tl_o.d_size[1:0] Yes Yes T2,T7,T9 Yes T2,T7,T9 OUTPUT
rom_tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
rom_tl_o.d_opcode[0] Yes Yes *T13,*T14,*T15 Yes T13,T14,T15 OUTPUT
rom_tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
rom_tl_o.d_valid Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
regs_tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_user.instr_type[3:0] Yes Yes T1,T9,T13 Yes T1,T3,T9 INPUT
regs_tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_address[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_source[7:0] Yes Yes T1,T2,T4 Yes T1,T2,T4 INPUT
regs_tl_i.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_opcode[2:0] Yes Yes T1,T3,T5 Yes T1,T3,T5 INPUT
regs_tl_i.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
regs_tl_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
regs_tl_o.d_error Yes Yes T13,T14,T15 Yes T13,T14,T15 OUTPUT
regs_tl_o.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
regs_tl_o.d_user.rsp_intg[5:0] Yes Yes *T1,*T2,*T4 Yes T1,T2,T4 OUTPUT
regs_tl_o.d_user.rsp_intg[6] Unreachable Unreachable Unreachable OUTPUT
regs_tl_o.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
regs_tl_o.d_sink Unreachable Unreachable Unreachable OUTPUT
regs_tl_o.d_source[7:0] Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
regs_tl_o.d_size[1:0] Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
regs_tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
regs_tl_o.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
regs_tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
regs_tl_o.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T1,T3,T4 Yes T1,T3,T4 INPUT
alert_rx_i[0].ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i[0].ping_p Unreachable Unreachable Unreachable INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T1,T3,T4 Yes T1,T3,T4 OUTPUT
pwrmgr_data_o.good[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
pwrmgr_data_o.done[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T4 OUTPUT
keymgr_data_o.valid Yes Yes T1,T2,T4 Yes T1,T2,T3 OUTPUT
keymgr_data_o.data[255:0] Yes Yes T1,T3,T4 Yes T1,T2,T3 OUTPUT
kmac_data_i.error No Yes T3,T25,T26 No INPUT
kmac_data_i.digest_share1[383:0] Yes Yes T1,T2,T4 Yes T1,T4,T18 INPUT
kmac_data_i.digest_share0[383:0] Yes Yes T1,T4,T11 Yes T1,T4,T18 INPUT
kmac_data_i.done Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
kmac_data_i.ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
kmac_data_o.last Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
kmac_data_o.strb[7:0] No No No OUTPUT
kmac_data_o.data[38:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
kmac_data_o.data[63:39] No No No OUTPUT
kmac_data_o.valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT

*Tests covering at least one bit in the range

Branch Coverage for Module : rom_ctrl
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 222 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv' or '../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 222 (tl_rom_h2d_upstream.a_valid) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T3


Assert Coverage for Module : rom_ctrl
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 29 29 100.00 23 79.31
Cover properties 0 0 0
Cover sequences 0 0 0
Total 29 29 100.00 23 79.31




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AlertTxOKnown_A 151035380 150898375 0 0
BusRomIndicesMatch_A 151023124 150892338 0 0
FpvSecCmFifoRptrCheck_A 151035380 0 0 0
FpvSecCmFifoWptrCheck_A 151035380 0 0 0
FpvSecCmRegWeOnehotCheck_A 151035380 60 0 0
KeymgrDataODataKnown_A 151035380 55928273 0 0
KeymgrDataODataKnown_AKnownEnable 151035380 150898375 0 0
KeymgrDataOValidKnown_A 151035380 150898375 0 0
KeymgrValidChk_A 151035380 0 0 236
KmacDataODataKnown_A 151035380 94873050 0 0
KmacDataODataKnown_AKnownEnable 151035380 150898375 0 0
KmacDataOValidKnown_A 151035380 150898375 0 0
PwrmgrDataChk_A 151035380 0 0 236
PwrmgrDataOKnown_A 151035380 150898375 0 0
RegsTlOAReadyKnown_A 151035380 150898375 0 0
RegsTlODDataKnown_A 151035380 6709909 0 0
RegsTlODDataKnown_AKnownEnable 151035380 150898375 0 0
RegsTlODValidKnown_A 151035380 150898375 0 0
RomTlOAReadyKnown_A 151035380 150898375 0 0
RomTlODDataKnown_A 151035380 10502741 0 0
RomTlODDataKnown_AKnownEnable 151035380 150898375 0 0
RomTlODValidKnown_A 151035380 150898375 0 0
StabilityChkKmac_A 151035380 94871126 0 0
StabilityChkkeymgr_A 151035380 55927333 0 0
TlAccessChk_A 151035380 94970102 0 0
gen_asserts_with_scrambling.FpvSecCmCheckerFsmAlert_A 151035380 60 0 0
gen_asserts_with_scrambling.FpvSecCmCompareAddrCtrCheck_A 151035380 0 0 0
gen_asserts_with_scrambling.FpvSecCmCompareFsmAlert_A 151035380 407 0 0
gen_fsm_scramble_enabled_asserts.BusLocalEscChk_A 151035380 0 0 0


AlertTxOKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 151035380 150898375 0 0
T1 167965 166217 0 0
T2 210900 210752 0 0
T3 358888 358750 0 0
T4 237942 237768 0 0
T5 24624 24541 0 0
T6 19318 16962 0 0
T7 54803 54710 0 0
T8 57452 57397 0 0
T9 355611 355489 0 0
T10 132223 132137 0 0

BusRomIndicesMatch_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 151023124 150892338 0 0
T1 167694 166161 0 0
T2 210900 210752 0 0
T3 358888 358750 0 0
T4 237933 237766 0 0
T5 24624 24541 0 0
T6 19318 16962 0 0
T7 54803 54710 0 0
T8 57452 57397 0 0
T9 355611 355489 0 0
T10 132223 132137 0 0

FpvSecCmFifoRptrCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 151035380 0 0 0

FpvSecCmFifoWptrCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 151035380 0 0 0

FpvSecCmRegWeOnehotCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 151035380 60 0 0
T6 19318 10 0 0
T7 54803 0 0 0
T8 57452 0 0 0
T9 355611 0 0 0
T10 132223 0 0 0
T11 239436 0 0 0
T12 201010 0 0 0
T13 552613 0 0 0
T18 167051 0 0 0
T29 0 20 0 0
T30 0 20 0 0
T32 0 10 0 0
T33 111426 0 0 0

KeymgrDataODataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 151035380 55928273 0 0
T1 167965 8378 0 0
T2 210900 6082 0 0
T3 358888 43 0 0
T4 237942 11862 0 0
T5 24624 61 0 0
T6 19318 140 0 0
T7 54803 1264 0 0
T8 57452 76 0 0
T9 355611 1612 0 0
T10 132223 1349 0 0

KeymgrDataODataKnown_AKnownEnable
NameAttemptsReal SuccessesFailuresIncomplete
Total 151035380 150898375 0 0
T1 167965 166217 0 0
T2 210900 210752 0 0
T3 358888 358750 0 0
T4 237942 237768 0 0
T5 24624 24541 0 0
T6 19318 16962 0 0
T7 54803 54710 0 0
T8 57452 57397 0 0
T9 355611 355489 0 0
T10 132223 132137 0 0

KeymgrDataOValidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 151035380 150898375 0 0
T1 167965 166217 0 0
T2 210900 210752 0 0
T3 358888 358750 0 0
T4 237942 237768 0 0
T5 24624 24541 0 0
T6 19318 16962 0 0
T7 54803 54710 0 0
T8 57452 57397 0 0
T9 355611 355489 0 0
T10 132223 132137 0 0

KeymgrValidChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 151035380 0 0 236

KmacDataODataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 151035380 94873050 0 0
T1 167965 157115 0 0
T2 210900 204469 0 0
T3 358888 358512 0 0
T4 237942 236443 0 0
T5 24624 24429 0 0
T6 19318 13819 0 0
T7 54803 53356 0 0
T8 57452 57240 0 0
T9 355611 353690 0 0
T10 132223 130716 0 0

KmacDataODataKnown_AKnownEnable
NameAttemptsReal SuccessesFailuresIncomplete
Total 151035380 150898375 0 0
T1 167965 166217 0 0
T2 210900 210752 0 0
T3 358888 358750 0 0
T4 237942 237768 0 0
T5 24624 24541 0 0
T6 19318 16962 0 0
T7 54803 54710 0 0
T8 57452 57397 0 0
T9 355611 355489 0 0
T10 132223 132137 0 0

KmacDataOValidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 151035380 150898375 0 0
T1 167965 166217 0 0
T2 210900 210752 0 0
T3 358888 358750 0 0
T4 237942 237768 0 0
T5 24624 24541 0 0
T6 19318 16962 0 0
T7 54803 54710 0 0
T8 57452 57397 0 0
T9 355611 355489 0 0
T10 132223 132137 0 0

PwrmgrDataChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 151035380 0 0 236

PwrmgrDataOKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 151035380 150898375 0 0
T1 167965 166217 0 0
T2 210900 210752 0 0
T3 358888 358750 0 0
T4 237942 237768 0 0
T5 24624 24541 0 0
T6 19318 16962 0 0
T7 54803 54710 0 0
T8 57452 57397 0 0
T9 355611 355489 0 0
T10 132223 132137 0 0

RegsTlOAReadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 151035380 150898375 0 0
T1 167965 166217 0 0
T2 210900 210752 0 0
T3 358888 358750 0 0
T4 237942 237768 0 0
T5 24624 24541 0 0
T6 19318 16962 0 0
T7 54803 54710 0 0
T8 57452 57397 0 0
T9 355611 355489 0 0
T10 132223 132137 0 0

RegsTlODDataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 151035380 6709909 0 0
T1 167965 72 0 0
T2 210900 96 0 0
T3 358888 1 0 0
T4 237942 87 0 0
T5 24624 19 0 0
T6 19318 10 0 0
T7 54803 0 0 0
T8 57452 10 0 0
T9 355611 32 0 0
T10 132223 0 0 0
T11 0 32 0 0
T18 0 38 0 0

RegsTlODDataKnown_AKnownEnable
NameAttemptsReal SuccessesFailuresIncomplete
Total 151035380 150898375 0 0
T1 167965 166217 0 0
T2 210900 210752 0 0
T3 358888 358750 0 0
T4 237942 237768 0 0
T5 24624 24541 0 0
T6 19318 16962 0 0
T7 54803 54710 0 0
T8 57452 57397 0 0
T9 355611 355489 0 0
T10 132223 132137 0 0

RegsTlODValidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 151035380 150898375 0 0
T1 167965 166217 0 0
T2 210900 210752 0 0
T3 358888 358750 0 0
T4 237942 237768 0 0
T5 24624 24541 0 0
T6 19318 16962 0 0
T7 54803 54710 0 0
T8 57452 57397 0 0
T9 355611 355489 0 0
T10 132223 132137 0 0

RomTlOAReadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 151035380 150898375 0 0
T1 167965 166217 0 0
T2 210900 210752 0 0
T3 358888 358750 0 0
T4 237942 237768 0 0
T5 24624 24541 0 0
T6 19318 16962 0 0
T7 54803 54710 0 0
T8 57452 57397 0 0
T9 355611 355489 0 0
T10 132223 132137 0 0

RomTlODDataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 151035380 10502741 0 0
T1 167965 9 0 0
T2 210900 213 0 0
T3 358888 0 0 0
T4 237942 3 0 0
T5 24624 0 0 0
T6 19318 0 0 0
T7 54803 224 0 0
T8 57452 0 0 0
T9 355611 189 0 0
T10 132223 347 0 0
T11 0 71 0 0
T12 0 294 0 0
T13 0 103608 0 0
T18 0 3 0 0

RomTlODDataKnown_AKnownEnable
NameAttemptsReal SuccessesFailuresIncomplete
Total 151035380 150898375 0 0
T1 167965 166217 0 0
T2 210900 210752 0 0
T3 358888 358750 0 0
T4 237942 237768 0 0
T5 24624 24541 0 0
T6 19318 16962 0 0
T7 54803 54710 0 0
T8 57452 57397 0 0
T9 355611 355489 0 0
T10 132223 132137 0 0

RomTlODValidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 151035380 150898375 0 0
T1 167965 166217 0 0
T2 210900 210752 0 0
T3 358888 358750 0 0
T4 237942 237768 0 0
T5 24624 24541 0 0
T6 19318 16962 0 0
T7 54803 54710 0 0
T8 57452 57397 0 0
T9 355611 355489 0 0
T10 132223 132137 0 0

StabilityChkKmac_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 151035380 94871126 0 0
T1 167965 157093 0 0
T2 210900 204467 0 0
T3 358888 358510 0 0
T4 237942 236440 0 0
T5 24624 24428 0 0
T6 19318 13788 0 0
T7 54803 53355 0 0
T8 57452 57239 0 0
T9 355611 353688 0 0
T10 132223 130715 0 0

StabilityChkkeymgr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 151035380 55927333 0 0
T1 167965 8361 0 0
T2 210900 6080 0 0
T3 358888 42 0 0
T4 237942 11852 0 0
T5 24624 60 0 0
T6 19318 133 0 0
T7 54803 1263 0 0
T8 57452 75 0 0
T9 355611 1610 0 0
T10 132223 1348 0 0

TlAccessChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 151035380 94970102 0 0
T1 167965 157839 0 0
T2 210900 204670 0 0
T3 358888 358707 0 0
T4 237942 236582 0 0
T5 24624 24480 0 0
T6 19318 16822 0 0
T7 54803 53446 0 0
T8 57452 57321 0 0
T9 355611 353877 0 0
T10 132223 130788 0 0

gen_asserts_with_scrambling.FpvSecCmCheckerFsmAlert_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 151035380 60 0 0
T6 19318 10 0 0
T7 54803 0 0 0
T8 57452 0 0 0
T9 355611 0 0 0
T10 132223 0 0 0
T11 239436 0 0 0
T12 201010 0 0 0
T13 552613 0 0 0
T18 167051 0 0 0
T29 0 20 0 0
T30 0 20 0 0
T32 0 10 0 0
T33 111426 0 0 0

gen_asserts_with_scrambling.FpvSecCmCompareAddrCtrCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 151035380 0 0 0

gen_asserts_with_scrambling.FpvSecCmCompareFsmAlert_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 151035380 407 0 0
T4 237942 10 0 0
T5 24624 0 0 0
T6 19318 10 0 0
T7 54803 0 0 0
T8 57452 0 0 0
T9 355611 0 0 0
T10 132223 0 0 0
T11 239436 0 0 0
T12 201010 0 0 0
T18 0 5 0 0
T22 0 20 0 0
T27 0 5 0 0
T28 0 25 0 0
T33 111426 0 0 0
T34 0 10 0 0
T35 0 10 0 0
T36 0 10 0 0
T37 0 10 0 0

gen_fsm_scramble_enabled_asserts.BusLocalEscChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 151035380 0 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%