Unified Coverage Report :: Module :: rom_ctrl_regs_reg_top

Module : rom_ctrl_regs_reg_top

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl_regs_reg_top.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg_regs	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg_regs

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.72	99.41	99.21	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.98	100.00	98.28	97.33		100.00	79.31	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_alert_test	100.00	100.00
u_chk	100.00	100.00		100.00			100.00
u_digest_0	100.00	100.00	100.00			100.00
u_digest_1	100.00	100.00	100.00			100.00
u_digest_2	100.00	100.00	100.00			100.00
u_digest_3	100.00	100.00	100.00			100.00
u_digest_4	100.00	100.00	100.00			100.00
u_digest_5	100.00	100.00	100.00			100.00
u_digest_6	100.00	100.00	100.00			100.00
u_digest_7	100.00	100.00	100.00			100.00
u_exp_digest_0	100.00	100.00	100.00			100.00
u_exp_digest_1	100.00	100.00	100.00			100.00
u_exp_digest_2	100.00	100.00	100.00			100.00
u_exp_digest_3	100.00	100.00	100.00			100.00
u_exp_digest_4	100.00	100.00	100.00			100.00
u_exp_digest_5	100.00	100.00	100.00			100.00
u_exp_digest_6	100.00	100.00	100.00			100.00
u_exp_digest_7	100.00	100.00	100.00			100.00
u_fatal_alert_cause_checker_error	100.00	100.00	100.00			100.00
u_fatal_alert_cause_integrity_error	100.00	100.00	100.00			100.00
u_prim_reg_we_check	100.00	100.00		100.00
u_reg_if	98.67	97.14	97.53			100.00	100.00
u_rsp_intg_gen	100.00	100.00					100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rom_ctrl_regs_reg_top

	Line No.	Total	Covered	Percent
TOTAL		76	76	100.00
ALWAYS	71	4	4	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	152	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
ALWAYS	692	19	19	100.00
CONT_ASSIGN	713	1	1	100.00
ALWAYS	717	1	1	100.00
CONT_ASSIGN	739	1	1	100.00
CONT_ASSIGN	741	1	1	100.00
ALWAYS	745	19	19	100.00
ALWAYS	768	21	21	100.00
CONT_ASSIGN	854	0	0
CONT_ASSIGN	862	1	1	100.00
CONT_ASSIGN	863	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl_regs_reg_top.sv' or '../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl_regs_reg_top.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
71	1	1
72	1	1
73	1	1
74	1	1
			MISSING_ELSE
80	1	1
92	1	1
93	1	1
121	1	1
122	1	1
152	1	1
166	1	1
692	1	1
693	1	1
694	1	1
695	1	1
696	1	1
697	1	1
698	1	1
699	1	1
700	1	1
701	1	1
702	1	1
703	1	1
704	1	1
705	1	1
706	1	1
707	1	1
708	1	1
709	1	1
710	1	1
713	1	1
717	1	1
739	1	1
741	1	1
745	1	1
746	1	1
747	1	1
748	1	1
749	1	1
750	1	1
751	1	1
752	1	1
753	1	1
754	1	1
755	1	1
756	1	1
757	1	1
758	1	1
759	1	1
760	1	1
761	1	1
762	1	1
763	1	1
768	1	1
769	1	1
771	1	1
775	1	1
776	1	1
780	1	1
784	1	1
788	1	1
792	1	1
796	1	1
800	1	1
804	1	1
808	1	1
812	1	1
816	1	1
820	1	1
824	1	1
828	1	1
832	1	1
836	1	1
840	1	1
854		unreachable
862	1	1
863	1	1

---

Cond Coverage for Module : rom_ctrl_regs_reg_top

	Total	Covered	Percent
Conditions	137	137	100.00
Logical	137	137	100.00
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (reg_we && ((!addrmiss)))
             ---1--    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T13,T14,T15
1	1	Covered	T5,T8,T13

 LINE       73
 EXPRESSION (intg_err || reg_we_err)
             ----1---    -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T29,T30
1	0	Covered	T48,T49,T50

 LINE       80
 EXPRESSION (err_q | intg_err | reg_we_err)
             --1--   ----2---   -----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T6,T29,T30
0	1	0	Covered	T48,T49,T50
1	0	0	Covered	T6,T29,T30

 LINE       122
 EXPRESSION ((devmode_i & addrmiss) | wr_err | intg_err)
             -----------1----------   ---2--   ----3---

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T48,T49,T50
0	1	0	Covered	T13,T14,T15
1	0	0	Covered	T13,T14,T15

 LINE       122
 SUB-EXPRESSION (devmode_i & addrmiss)
                 ----1----   ----2---

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Covered	T13,T14,T15

 LINE       693
 EXPRESSION (reg_addr == rom_ctrl_reg_pkg::ROM_CTRL_ALERT_TEST_OFFSET)
            -----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T5,T8

 LINE       694
 EXPRESSION (reg_addr == rom_ctrl_reg_pkg::ROM_CTRL_FATAL_ALERT_CAUSE_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       695
 EXPRESSION (reg_addr == rom_ctrl_reg_pkg::ROM_CTRL_DIGEST_0_OFFSET)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T9

 LINE       696
 EXPRESSION (reg_addr == rom_ctrl_reg_pkg::ROM_CTRL_DIGEST_1_OFFSET)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       697
 EXPRESSION (reg_addr == rom_ctrl_reg_pkg::ROM_CTRL_DIGEST_2_OFFSET)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T9

 LINE       698
 EXPRESSION (reg_addr == rom_ctrl_reg_pkg::ROM_CTRL_DIGEST_3_OFFSET)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T9

 LINE       699
 EXPRESSION (reg_addr == rom_ctrl_reg_pkg::ROM_CTRL_DIGEST_4_OFFSET)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T9

 LINE       700
 EXPRESSION (reg_addr == rom_ctrl_reg_pkg::ROM_CTRL_DIGEST_5_OFFSET)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T9,T11

 LINE       701
 EXPRESSION (reg_addr == rom_ctrl_reg_pkg::ROM_CTRL_DIGEST_6_OFFSET)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T9

 LINE       702
 EXPRESSION (reg_addr == rom_ctrl_reg_pkg::ROM_CTRL_DIGEST_7_OFFSET)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T9,T11

 LINE       703
 EXPRESSION (reg_addr == rom_ctrl_reg_pkg::ROM_CTRL_EXP_DIGEST_0_OFFSET)
            ------------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T9,T11

 LINE       704
 EXPRESSION (reg_addr == rom_ctrl_reg_pkg::ROM_CTRL_EXP_DIGEST_1_OFFSET)
            ------------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T9

 LINE       705
 EXPRESSION (reg_addr == rom_ctrl_reg_pkg::ROM_CTRL_EXP_DIGEST_2_OFFSET)
            ------------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T9,T11

 LINE       706
 EXPRESSION (reg_addr == rom_ctrl_reg_pkg::ROM_CTRL_EXP_DIGEST_3_OFFSET)
            ------------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       707
 EXPRESSION (reg_addr == rom_ctrl_reg_pkg::ROM_CTRL_EXP_DIGEST_4_OFFSET)
            ------------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T9

 LINE       708
 EXPRESSION (reg_addr == rom_ctrl_reg_pkg::ROM_CTRL_EXP_DIGEST_5_OFFSET)
            ------------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T9,T11

 LINE       709
 EXPRESSION (reg_addr == rom_ctrl_reg_pkg::ROM_CTRL_EXP_DIGEST_6_OFFSET)
            ------------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T9

 LINE       710
 EXPRESSION (reg_addr == rom_ctrl_reg_pkg::ROM_CTRL_EXP_DIGEST_7_OFFSET)
            ------------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T9

 LINE       713
 EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
             ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       713
 SUB-EXPRESSION (reg_re || reg_we)
                 ---1--    ---2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T8,T13
1	0	Covered	T1,T2,T3

 LINE       717
 EXPRESSION 
 Number  Term
      1  reg_we & 
      2  ((addr_hit[0] & ((|(4'b1 & (~reg_be))))) | (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | (addr_hit[2] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[3] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[4] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[5] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[6] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[7] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[8] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[9] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[10] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[11] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[12] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[13] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[14] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[15] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[16] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[17] & ((|(4'b1111 & (~reg_be)))))))

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T8,T13
1	1	Covered	T13,T14,T15

 LINE       717
 SUB-EXPRESSION 
 Number  Term
      1  (addr_hit[0] & ((|(4'b1 & (~reg_be))))) | 
      2  (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | 
      3  (addr_hit[2] & ((|(4'b1111 & (~reg_be))))) | 
      4  (addr_hit[3] & ((|(4'b1111 & (~reg_be))))) | 
      5  (addr_hit[4] & ((|(4'b1111 & (~reg_be))))) | 
      6  (addr_hit[5] & ((|(4'b1111 & (~reg_be))))) | 
      7  (addr_hit[6] & ((|(4'b1111 & (~reg_be))))) | 
      8  (addr_hit[7] & ((|(4'b1111 & (~reg_be))))) | 
      9  (addr_hit[8] & ((|(4'b1111 & (~reg_be))))) | 
     10  (addr_hit[9] & ((|(4'b1111 & (~reg_be))))) | 
     11  (addr_hit[10] & ((|(4'b1111 & (~reg_be))))) | 
     12  (addr_hit[11] & ((|(4'b1111 & (~reg_be))))) | 
     13  (addr_hit[12] & ((|(4'b1111 & (~reg_be))))) | 
     14  (addr_hit[13] & ((|(4'b1111 & (~reg_be))))) | 
     15  (addr_hit[14] & ((|(4'b1111 & (~reg_be))))) | 
     16  (addr_hit[15] & ((|(4'b1111 & (~reg_be))))) | 
     17  (addr_hit[16] & ((|(4'b1111 & (~reg_be))))) | 
     18  (addr_hit[17] & ((|(4'b1111 & (~reg_be))))))

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	-17-	-18-	Status	Tests
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	Covered	T1,T2,T3
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	Covered	T1,T2,T9
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	Covered	T1,T2,T9
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	Covered	T2,T9,T13
0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	0	Covered	T1,T2,T9
0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	0	0	Covered	T1,T2,T3
0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	Covered	T2,T9,T13
0	0	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	Covered	T1,T2,T11
0	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	Covered	T2,T9,T11
0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	Covered	T2,T9,T11
0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	Covered	T1,T2,T9
0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	Covered	T2,T9,T11
0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	0	Covered	T1,T2,T9
0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	Covered	T1,T11,T13
0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	Covered	T1,T2,T9
0	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	Covered	T1,T2,T3
0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	Covered	T1,T2,T9
0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	Covered	T1,T4,T18
1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	Covered	T1,T9,T13

 LINE       717
 SUB-EXPRESSION (addr_hit[0] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T8,T13
1	1	Covered	T1,T9,T13

 LINE       717
 SUB-EXPRESSION (addr_hit[1] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T4,T18

 LINE       717
 SUB-EXPRESSION (addr_hit[2] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T9,T11
1	1	Covered	T1,T2,T9

 LINE       717
 SUB-EXPRESSION (addr_hit[3] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T9,T13
1	1	Covered	T1,T2,T3

 LINE       717
 SUB-EXPRESSION (addr_hit[4] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T9,T11
1	1	Covered	T1,T2,T9

 LINE       717
 SUB-EXPRESSION (addr_hit[5] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T9,T13
1	1	Covered	T1,T11,T13

 LINE       717
 SUB-EXPRESSION (addr_hit[6] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T9
1	1	Covered	T1,T2,T9

 LINE       717
 SUB-EXPRESSION (addr_hit[7] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T9,T11
1	1	Covered	T2,T9,T11

 LINE       717
 SUB-EXPRESSION (addr_hit[8] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T9,T11
1	1	Covered	T1,T2,T9

 LINE       717
 SUB-EXPRESSION (addr_hit[9] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T9,T11
1	1	Covered	T2,T9,T11

 LINE       717
 SUB-EXPRESSION (addr_hit[10] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T9,T11
1	1	Covered	T2,T9,T11

 LINE       717
 SUB-EXPRESSION (addr_hit[11] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T9
1	1	Covered	T1,T2,T11

 LINE       717
 SUB-EXPRESSION (addr_hit[12] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T9,T11
1	1	Covered	T2,T9,T13

 LINE       717
 SUB-EXPRESSION (addr_hit[13] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T9,T11
1	1	Covered	T1,T2,T3

 LINE       717
 SUB-EXPRESSION (addr_hit[14] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T9,T11
1	1	Covered	T1,T2,T9

 LINE       717
 SUB-EXPRESSION (addr_hit[15] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T9,T11
1	1	Covered	T2,T9,T13

 LINE       717
 SUB-EXPRESSION (addr_hit[16] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T9,T13
1	1	Covered	T1,T2,T9

 LINE       717
 SUB-EXPRESSION (addr_hit[17] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T9,T13
1	1	Covered	T1,T2,T9

 LINE       739
 EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T51,T52,T48
1	0	1	Covered	T1,T5,T8
1	1	0	Covered	T13,T14,T15
1	1	1	Covered	T5,T8,T31

---

Branch Coverage for Module : rom_ctrl_regs_reg_top

	Line No.	Total	Covered	Percent
Branches		24	24	100.00
TERNARY	713	2	2	100.00
IF	71	3	3	100.00
CASE	769	19	19	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl_regs_reg_top.sv' or '../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl_regs_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	713	((reg_re || reg_we)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	71	if ((!rst_ni))
-2-:	73	if ((intg_err || reg_we_err))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T6,T29,T30
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	769	case (1'b1)

Branches:

-1-	Status	Tests
addr_hit[0]	Covered	T1,T2,T4
addr_hit[1]	Covered	T1,T2,T3
addr_hit[2]	Covered	T1,T2,T4
addr_hit[3]	Covered	T1,T2,T3
addr_hit[4]	Covered	T1,T2,T4
addr_hit[5]	Covered	T1,T2,T4
addr_hit[6]	Covered	T1,T2,T4
addr_hit[7]	Covered	T2,T4,T5
addr_hit[8]	Covered	T1,T2,T4
addr_hit[9]	Covered	T2,T4,T5
addr_hit[10]	Covered	T2,T4,T5
addr_hit[11]	Covered	T1,T2,T4
addr_hit[12]	Covered	T2,T4,T5
addr_hit[13]	Covered	T1,T2,T3
addr_hit[14]	Covered	T1,T2,T4
addr_hit[15]	Covered	T2,T4,T5
addr_hit[16]	Covered	T1,T2,T4
addr_hit[17]	Covered	T1,T2,T4
default	Covered	T1,T2,T3

---

Assert Coverage for Module : rom_ctrl_regs_reg_top

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
en2addrHit	189252270	123086	0	0
reAfterRv	189252270	123085	0	0
rePulse	189252270	31238	0	0
wePulse	189252270	91847	0	0

en2addrHit

Name	Attempts	Real Successes	Failures	Incomplete
Total	189252270	123086	0	0
T1	167965	18	0	0
T2	210900	96	0	0
T3	358888	1	0	0
T4	237942	21	0	0
T5	24624	19	0	0
T6	19318	10	0	0
T7	54803	0	0	0
T8	57452	10	0	0
T9	355611	32	0	0
T10	132223	0	0	0
T11	0	32	0	0
T18	0	38	0	0

reAfterRv

Name	Attempts	Real Successes	Failures	Incomplete
Total	189252270	123085	0	0
T1	167965	18	0	0
T2	210900	96	0	0
T3	358888	1	0	0
T4	237942	21	0	0
T5	24624	19	0	0
T6	19318	10	0	0
T7	54803	0	0	0
T8	57452	10	0	0
T9	355611	32	0	0
T10	132223	0	0	0
T11	0	32	0	0
T18	0	38	0	0

rePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	189252270	31238	0	0
T1	167965	18	0	0
T2	210900	96	0	0
T3	358888	1	0	0
T4	237942	21	0	0
T5	24624	0	0	0
T6	19318	10	0	0
T7	54803	0	0	0
T8	57452	0	0	0
T9	355611	32	0	0
T10	132223	0	0	0
T11	0	32	0	0
T13	0	1429	0	0
T18	0	38	0	0
T25	0	1	0	0

wePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	189252270	91847	0	0
T5	24624	19	0	0
T6	19318	0	0	0
T7	54803	0	0	0
T8	57452	10	0	0
T9	355611	0	0	0
T10	132223	0	0	0
T11	239436	0	0	0
T12	201010	0	0	0
T13	0	6188	0	0
T14	0	2761	0	0
T15	0	3161	0	0
T18	167051	0	0	0
T31	0	10	0	0
T33	111426	0	0	0
T38	0	2897	0	0
T53	0	8	0	0
T54	0	6	0	0
T55	0	13	0	0