Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : rom_ctrl_compare
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.07 100.00 95.35 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl_compare.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.gen_fsm_scramble_enabled.u_checker_fsm.u_compare 99.07 100.00 95.35 100.00 100.00 100.00


Module Instance : tb.dut.gen_fsm_scramble_enabled.u_checker_fsm.u_compare

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.07 100.00 95.35 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.56 100.00 95.35 90.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.67 100.00 96.36 100.00 96.97 75.00 gen_fsm_scramble_enabled.u_checker_fsm


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_done_sender 100.00 100.00 100.00 100.00
u_prim_count_addr 90.00 90.00
u_state_regs 100.00 100.00 100.00 100.00

Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : rom_ctrl_compare
Line No.TotalCoveredPercent
TOTAL2424100.00
ALWAYS8533100.00
ALWAYS8877100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN11411100.00
CONT_ASSIGN12011100.00
CONT_ASSIGN12511100.00
CONT_ASSIGN14711100.00
CONT_ASSIGN14811100.00
CONT_ASSIGN14911100.00
CONT_ASSIGN15111100.00
ALWAYS15344100.00
CONT_ASSIGN16211100.00
CONT_ASSIGN17611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl_compare.sv' or '../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl_compare.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
85 3 3
88 1 1
89 1 1
90 1 1
92 2 2
MISSING_ELSE
95 2 2
MISSING_ELSE
108 1 1
114 1 1
120 1 1
125 1 1
147 1 1
148 1 1
149 1 1
151 1 1
153 1 1
154 1 1
156 1 1
157 1 1
MISSING_ELSE
162 1 1
176 1 1

Cond Coverage for Module : rom_ctrl_compare
TotalCoveredPercent
Conditions434195.35
Logical434195.35
Non-Logical00
Event00

 LINE       95
 EXPRESSION (addr_q == LastAddr)
            ----------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       108
 EXPRESSION (start_i && (state_q != Waiting))
             ---1---    ----------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T4,T18 

 LINE       108
 SUB-EXPRESSION (state_q != Waiting)
                ----------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       114
 EXPRESSION ((state_q == Waiting) && (addr_q != '0))
             ----------1---------    -------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T18,T28 

 LINE       114
 SUB-EXPRESSION (state_q == Waiting)
                ----------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       114
 SUB-EXPRESSION (addr_q != '0)
                -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       120
 EXPRESSION ((state_q == Done) && (addr_q != LastAddr))
             --------1--------    ----------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T18,T28 

 LINE       120
 SUB-EXPRESSION (state_q == Done)
                --------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       120
 SUB-EXPRESSION (addr_q != LastAddr)
                ----------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       125
 EXPRESSION ((state_q == Checking) && (addr_q != LastAddr))
             ----------1----------    ----------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3 

 LINE       125
 SUB-EXPRESSION (state_q == Checking)
                ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       125
 SUB-EXPRESSION (addr_q != LastAddr)
                ----------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       151
 EXPRESSION (matches_q && (digest_word == exp_digest_word))
             ----1----    ----------------2---------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3 

 LINE       151
 SUB-EXPRESSION (digest_word == exp_digest_word)
                ----------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       156
 EXPRESSION (state_q == Checking)
            ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       162
 EXPRESSION (state_q == Done)
            --------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       176
 EXPRESSION (fsm_alert | start_alert | wait_addr_alert | done_addr_alert | addr_ctr_alert)
             ----1----   -----2-----   -------3-------   -------4-------   -------5------
-1--2--3--4--5-StatusTests
00000CoveredT1,T2,T3
00001Not Covered
00010CoveredT1,T18,T28
00100CoveredT1,T18,T28
01000CoveredT1,T4,T18
10000CoveredT4,T6,T18
FSM Coverage for Module : rom_ctrl_compare
Summary for FSM :: state_q
TotalCoveredPercent
States 3 3 100.00 (Not included in score)
Transitions 2 2 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
Checking 92 Covered T1,T2,T3
Done 95 Covered T1,T2,T3
Waiting 91 Covered T1,T2,T3


transitionsLine No.CoveredTests
Checking->Done 95 Covered T1,T2,T3
Waiting->Checking 92 Covered T1,T2,T3


Branch Coverage for Module : rom_ctrl_compare
Line No.TotalCoveredPercent
Branches 11 11 100.00
IF 85 2 2 100.00
CASE 90 6 6 100.00
IF 153 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl_compare.sv' or '../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl_compare.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	85	if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	90	case (state_q)
-2-:	92	if (start_i)
-3-:	95	if ((addr_q == LastAddr))

Branches:
-1--2--3-StatusTests
Waiting 1 - Covered T1,T2,T3
Waiting 0 - Covered T1,T2,T3
Checking - 1 Covered T1,T2,T3
Checking - 0 Covered T1,T2,T3
Done - - Covered T1,T2,T3
default - - Covered T4,T6,T18 



	LineNo.	Expression
-1-:	153	if ((!rst_ni))
-2-:	156	if ((state_q == Checking))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3

Assert Coverage for Module : rom_ctrl_compare
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumWordsPositive_A 236 236 0 0
u_state_regs_A 151035380 150898375 0 0


NumWordsPositive_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 236 236 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 151035380 150898375 0 0
T1 167965 166217 0 0
T2 210900 210752 0 0
T3 358888 358750 0 0
T4 237942 237768 0 0
T5 24624 24541 0 0
T6 19318 16962 0 0
T7 54803 54710 0 0
T8 57452 57397 0 0
T9 355611 355489 0 0
T10 132223 132137 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%