Unified Coverage Report :: Module :: rom_ctrl

Module : rom_ctrl

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.98	100.00	98.28	97.33		100.00	79.31

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	94.98	100.00	98.28	97.33		100.00	79.31

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.98	100.00	98.28	97.33		100.00	79.31

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.31	97.04	92.65	97.88	100.00	98.37	97.89

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_alert_tx[0].u_alert_sender	100.00			100.00
gen_fsm_scramble_enabled.u_checker_fsm	95.92	100.00	96.30	90.00	100.00	98.31	90.91
gen_rom_scramble_enabled.u_rom	97.06	88.24		100.00		100.00	100.00
regs_tlul_assert_device	100.00	100.00				100.00	100.00
rom_ctrl_regs_csr_assert	100.00						100.00
rom_tlul_assert_device	99.18	100.00				100.00	97.55
u_mux	95.24	100.00	85.71			100.00
u_reg_regs	99.72	99.41	99.21	100.00		100.00	100.00
u_rom_top	100.00	100.00				100.00	100.00
u_tl_adapter_rom	93.77	91.56	83.06	99.07		95.18	100.00
u_tl_rom_h2d_buf	100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rom_ctrl

	Line No.	Total	Covered	Percent
TOTAL		65	65	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	123	1	1	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	220	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
CONT_ASSIGN	321	1	1	100.00
CONT_ASSIGN	422	1	1	100.00
CONT_ASSIGN	422	1	1	100.00
CONT_ASSIGN	422	1	1	100.00
CONT_ASSIGN	422	1	1	100.00
CONT_ASSIGN	422	1	1	100.00
CONT_ASSIGN	422	1	1	100.00
CONT_ASSIGN	422	1	1	100.00
CONT_ASSIGN	422	1	1	100.00
CONT_ASSIGN	423	1	1	100.00
CONT_ASSIGN	423	1	1	100.00
CONT_ASSIGN	423	1	1	100.00
CONT_ASSIGN	423	1	1	100.00
CONT_ASSIGN	423	1	1	100.00
CONT_ASSIGN	423	1	1	100.00
CONT_ASSIGN	423	1	1	100.00
CONT_ASSIGN	423	1	1	100.00
CONT_ASSIGN	425	1	1	100.00
CONT_ASSIGN	425	1	1	100.00
CONT_ASSIGN	425	1	1	100.00
CONT_ASSIGN	425	1	1	100.00
CONT_ASSIGN	425	1	1	100.00
CONT_ASSIGN	425	1	1	100.00
CONT_ASSIGN	425	1	1	100.00
CONT_ASSIGN	425	1	1	100.00
CONT_ASSIGN	426	1	1	100.00
CONT_ASSIGN	426	1	1	100.00
CONT_ASSIGN	426	1	1	100.00
CONT_ASSIGN	426	1	1	100.00
CONT_ASSIGN	426	1	1	100.00
CONT_ASSIGN	426	1	1	100.00
CONT_ASSIGN	426	1	1	100.00
CONT_ASSIGN	426	1	1	100.00
CONT_ASSIGN	428	1	1	100.00
CONT_ASSIGN	428	1	1	100.00
CONT_ASSIGN	428	1	1	100.00
CONT_ASSIGN	428	1	1	100.00
CONT_ASSIGN	428	1	1	100.00
CONT_ASSIGN	428	1	1	100.00
CONT_ASSIGN	428	1	1	100.00
CONT_ASSIGN	428	1	1	100.00
CONT_ASSIGN	429	1	1	100.00
CONT_ASSIGN	429	1	1	100.00
CONT_ASSIGN	429	1	1	100.00
CONT_ASSIGN	429	1	1	100.00
CONT_ASSIGN	429	1	1	100.00
CONT_ASSIGN	429	1	1	100.00
CONT_ASSIGN	429	1	1	100.00
CONT_ASSIGN	429	1	1	100.00
CONT_ASSIGN	433	1	1	100.00
CONT_ASSIGN	435	1	1	100.00
CONT_ASSIGN	438	1	1	100.00
CONT_ASSIGN	439	1	1	100.00
CONT_ASSIGN	440	1	1	100.00
CONT_ASSIGN	441	1	1	100.00
CONT_ASSIGN	446	1	1	100.00
CONT_ASSIGN	450	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv' or '../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
117	1	1
122	1	1
123	1	1
124	1	1
125	1	1
128	1	1
220	1	1
266	1	1
321	1	1
422	8	8
423	8	8
425	8	8
426	8	8
428	8	8
429	8	8
433	1	1
435	1	1
438	1	1
439	1	1
440	1	1
441	1	1
446	1	1
450	1	1

---

Cond Coverage for Module : rom_ctrl

	Total	Covered	Percent
Conditions	58	57	98.28
Logical	58	57	98.28
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (tl_rom_h2d_upstream.a_valid ? tl_rom_h2d_upstream.a_address[2+:RomIndexWidth] : '0)
             -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       266
 EXPRESSION (bus_rom_rvalid_raw & ((!internal_alert)))
             ---------1--------   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T18,T27,T28
1	1	Covered	T4,T5,T6

 LINE       426
 EXPRESSION (exp_digest_de && (0[2:0] == exp_digest_idx))
             ------1------    -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       426
 SUB-EXPRESSION (0[2:0] == exp_digest_idx)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       426
 EXPRESSION (exp_digest_de && (1[2:0] == exp_digest_idx))
             ------1------    -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       426
 SUB-EXPRESSION (1[2:0] == exp_digest_idx)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       426
 EXPRESSION (exp_digest_de && (2[2:0] == exp_digest_idx))
             ------1------    -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       426
 SUB-EXPRESSION (2[2:0] == exp_digest_idx)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       426
 EXPRESSION (exp_digest_de && (3[2:0] == exp_digest_idx))
             ------1------    -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       426
 SUB-EXPRESSION (3[2:0] == exp_digest_idx)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       426
 EXPRESSION (exp_digest_de && (4[2:0] == exp_digest_idx))
             ------1------    -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       426
 SUB-EXPRESSION (4[2:0] == exp_digest_idx)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       426
 EXPRESSION (exp_digest_de && (5[2:0] == exp_digest_idx))
             ------1------    -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       426
 SUB-EXPRESSION (5[2:0] == exp_digest_idx)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       426
 EXPRESSION (exp_digest_de && (6[2:0] == exp_digest_idx))
             ------1------    -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       426
 SUB-EXPRESSION (6[2:0] == exp_digest_idx)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       426
 EXPRESSION (exp_digest_de && (7[2:0] == exp_digest_idx))
             ------1------    -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       426
 SUB-EXPRESSION (7[2:0] == exp_digest_idx)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       433
 EXPRESSION (rom_reg_integrity_error | rom_integrity_error | reg_integrity_error)
             -----------1-----------   ---------2---------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T2,T40,T41
0	1	0	Not Covered
1	0	0	Unreachable

 LINE       435
 EXPRESSION (checker_alert | mux_alert)
             ------1------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T18,T27,T28
1	0	Covered	T2,T3,T7

 LINE       446
 EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
             ---------1---------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T42,T43
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T44,T42

 LINE       450
 EXPRESSION (bus_integrity_error | checker_alert | mux_alert)
             ---------1---------   ------2------   ----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T18,T27,T28
0	1	0	Covered	T2,T3,T7
1	0	0	Covered	T2,T40,T41

---

Toggle Coverage for Module : rom_ctrl

	Total	Covered	Percent
Totals	61	56	91.80
Total Bits	2882	2805	97.33
Total Bits 0->1	1441	1402	97.29
Total Bits 1->0	1441	1403	97.36

Ports	61	56	91.80
Port Bits	2882	2805	97.33
Port Bits 0->1	1441	1402	97.29
Port Bits 1->0	1441	1403	97.36

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	INPUT
rst_ni	Yes	Yes	T36,T37,T45	Yes	T30,T31,T32	INPUT
rom_cfg_i.cfg[3:0]	No	No		No		INPUT
rom_cfg_i.cfg_en	No	No		No		INPUT
rom_tl_i.d_ready	Yes	Yes	T30,T32,T33	Yes	T30,T31,T32	INPUT
rom_tl_i.a_user.data_intg[6:0]	Yes	Yes	T31,T34,T36	Yes	T34,T36,T39	INPUT
rom_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T31,T34,T36	Yes	T34,T36,T39	INPUT
rom_tl_i.a_user.instr_type[3:0]	Yes	Yes	T34,T36,T39	Yes	T34,T36,T39	INPUT
rom_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
rom_tl_i.a_data[31:0]	Yes	Yes	T31,T34,T36	Yes	T34,T36,T39	INPUT
rom_tl_i.a_mask[3:0]	Yes	Yes	T32,T34,T36	Yes	T34,T36,T39	INPUT
rom_tl_i.a_address[31:0]	Yes	Yes	T31,T32,T34	Yes	T34,T36,T39	INPUT
rom_tl_i.a_source[7:0]	Yes	Yes	T31,T34,T36	Yes	T34,T36,T39	INPUT
rom_tl_i.a_size[1:0]	Yes	Yes	T34,T36,T39	Yes	T32,T34,T36	INPUT
rom_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
rom_tl_i.a_opcode[2:0]	Yes	Yes	T34,T36,T39	Yes	T32,T34,T36	INPUT
rom_tl_i.a_valid	Yes	Yes	T34,T36,T39	Yes	T34,T36,T39	INPUT
rom_tl_o.a_ready	Yes	Yes	T34,T36,T37	Yes	T30,T31,T32	OUTPUT
rom_tl_o.d_error	Yes	Yes	T34,T36,T39	Yes	T34,T36,T39	OUTPUT
rom_tl_o.d_user.data_intg[6:0]	Yes	Yes	T45,T46,T47	Yes	T45,T46,T47	OUTPUT
rom_tl_o.d_user.rsp_intg[5:0]	Yes	Yes	T34,T36,T39	Yes	T34,T36,T39	OUTPUT
rom_tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
rom_tl_o.d_data[31:0]	Yes	Yes	T34,T36,T39	Yes	T34,T36,T39	OUTPUT
rom_tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
rom_tl_o.d_source[7:0]	Yes	Yes	T34,T36,T39	Yes	T34,T36,T39	OUTPUT
rom_tl_o.d_size[1:0]	Yes	Yes	T34,T36,T39	Yes	T34,T36,T39	OUTPUT
rom_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
rom_tl_o.d_opcode[0]	Yes	Yes	*T34,*T36,*T39	Yes	T34,T36,T39	OUTPUT
rom_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
rom_tl_o.d_valid	Yes	Yes	T34,T36,T39	Yes	T34,T36,T39	OUTPUT
regs_tl_i.d_ready	Yes	Yes	T30,T32,T33	Yes	T30,T31,T32	INPUT
regs_tl_i.a_user.data_intg[6:0]	Yes	Yes	T30,T31,T32	Yes	T31,T32,T33	INPUT
regs_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T31,T32,T33	Yes	T30,T31,T32	INPUT
regs_tl_i.a_user.instr_type[3:0]	Yes	Yes	T30,T34,T36	Yes	T34,T36,T39	INPUT
regs_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_data[31:0]	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	INPUT
regs_tl_i.a_mask[3:0]	Yes	Yes	T30,T32,T34	Yes	T34,T36,T39	INPUT
regs_tl_i.a_address[31:0]	Yes	Yes	T34,T36,T39	Yes	T34,T36,T39	INPUT
regs_tl_i.a_source[7:0]	Yes	Yes	T31,T32,T33	Yes	T30,T31,T32	INPUT
regs_tl_i.a_size[1:0]	Yes	Yes	T30,T32,T34	Yes	T32,T34,T36	INPUT
regs_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_opcode[2:0]	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	INPUT
regs_tl_i.a_valid	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	INPUT
regs_tl_o.a_ready	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
regs_tl_o.d_error	Yes	Yes	T36,T48,T49	Yes	T34,T36,T39	OUTPUT
regs_tl_o.d_user.data_intg[6:0]	Yes	Yes	T3,T7,T4	Yes	T3,T7,T4	OUTPUT
regs_tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T31,*T32,*T33	Yes	T31,T32,T33	OUTPUT
regs_tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_data[31:0]	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
regs_tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_source[7:0]	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
regs_tl_o.d_size[1:0]	Yes	Yes	T32,T34,T36	Yes	T32,T34,T36	OUTPUT
regs_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_opcode[0]	Yes	Yes	*T31,*T32,*T34	Yes	T31,T32,T33	OUTPUT
regs_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_valid	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T31,T32,T36	Yes	T31,T32,T36	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T31,T32,T36	Yes	T31,T32,T36	OUTPUT
pwrmgr_data_o.good[3:0]	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
pwrmgr_data_o.done[3:0]	Yes	Yes	T30,T31,T32	Yes	T45,T46,T47	OUTPUT
keymgr_data_o.valid	Yes	Yes	T45,T46,T47	Yes	T30,T31,T32	OUTPUT
keymgr_data_o.data[255:0]	Yes	Yes	T45,T46,T47	Yes	T31,T32,T34	OUTPUT
kmac_data_i.error	No	Yes	T3,T7,T20	No		INPUT
kmac_data_i.digest_share1[383:0]	Yes	Yes	T45,T46,T47	Yes	T45,T46,T47	INPUT
kmac_data_i.digest_share0[383:0]	Yes	Yes	T45,T46,T47	Yes	T45,T46,T47	INPUT
kmac_data_i.done	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	INPUT
kmac_data_i.ready	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	INPUT
kmac_data_o.last	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
kmac_data_o.strb[7:0]	No	No		No		OUTPUT
kmac_data_o.data[38:0]	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
kmac_data_o.data[63:39]	No	No		No		OUTPUT
kmac_data_o.valid	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Module : rom_ctrl

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
TERNARY	220	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv' or '../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	220	(tl_rom_h2d_upstream.a_valid) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

---

Assert Coverage for Module : rom_ctrl

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	29	29	100.00	23	79.31
Cover properties	0	0		0
Cover sequences	0	0		0
Total	29	29	100.00	23	79.31

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxOKnown_A	248824395	248642368	0	0
BusRomIndicesMatch_A	248809963	248635024	0	0
FpvSecCmFifoRptrCheck_A	248824395	0	0	0
FpvSecCmFifoWptrCheck_A	248824395	0	0	0
FpvSecCmRegWeOnehotCheck_A	248824395	80	0	0
KeymgrDataODataKnown_A	248824395	98442242	0	0
KeymgrDataODataKnown_AKnownEnable	248824395	248642368	0	0
KeymgrDataOValidKnown_A	248824395	248642368	0	0
KeymgrValidChk_A	248824395	0	0	332
KmacDataODataKnown_A	248824395	150066344	0	0
KmacDataODataKnown_AKnownEnable	248824395	248642368	0	0
KmacDataOValidKnown_A	248824395	248642368	0	0
PwrmgrDataChk_A	248824395	0	0	332
PwrmgrDataOKnown_A	248824395	248642368	0	0
RegsTlOAReadyKnown_A	248824395	248642368	0	0
RegsTlODDataKnown_A	248824395	14786257	0	0
RegsTlODDataKnown_AKnownEnable	248824395	248642368	0	0
RegsTlODValidKnown_A	248824395	248642368	0	0
RomTlOAReadyKnown_A	248824395	248642368	0	0
RomTlODDataKnown_A	248824395	21837727	0	0
RomTlODDataKnown_AKnownEnable	248824395	248642368	0	0
RomTlODValidKnown_A	248824395	248642368	0	0
StabilityChkKmac_A	248824395	150063719	0	0
StabilityChkkeymgr_A	248824395	98440927	0	0
TlAccessChk_A	248824395	150200126	0	0
gen_asserts_with_scrambling.FpvSecCmCheckerFsmAlert_A	248824395	80	0	0
gen_asserts_with_scrambling.FpvSecCmCompareAddrCtrCheck_A	248824395	0	0	0
gen_asserts_with_scrambling.FpvSecCmCompareFsmAlert_A	248824395	561	0	0
gen_fsm_scramble_enabled_asserts.BusLocalEscChk_A	248824395	0	0	0

AlertTxOKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	248824395	248642368	0	0
T1	147933	147838	0	0
T2	212398	207805	0	0
T3	190036	189907	0	0
T4	178672	178663	0	0
T5	297393	297258	0	0
T6	113827	113812	0	0
T7	98571	98454	0	0
T8	159075	158999	0	0
T9	189937	189863	0	0
T10	362843	362651	0	0

BusRomIndicesMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	248809963	248635024	0	0
T1	147933	147838	0	0
T2	212398	207805	0	0
T3	190036	189907	0	0
T4	178672	178663	0	0
T5	297393	297258	0	0
T6	113827	113812	0	0
T7	98571	98454	0	0
T8	159075	158999	0	0
T9	189937	189863	0	0
T10	362843	362651	0	0

FpvSecCmFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	248824395	0	0	0

FpvSecCmFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	248824395	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	248824395	80	0	0
T2	212398	20	0	0
T3	190036	0	0	0
T4	178672	0	0	0
T5	297393	0	0	0
T6	113827	0	0	0
T7	98571	0	0	0
T8	159075	0	0	0
T9	189937	0	0	0
T10	362843	0	0	0
T20	392149	0	0	0
T40	0	10	0	0
T41	0	20	0	0
T50	0	20	0	0
T51	0	10	0	0

KeymgrDataODataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	248824395	98442242	0	0
T1	147933	137	0	0
T2	212398	31	0	0
T3	190036	61	0	0
T4	178672	171242	0	0
T5	297393	1402	0	0
T6	113827	598123	0	0
T7	98571	53	0	0
T8	159075	289	0	0
T9	189937	839	0	0
T10	362843	1483	0	0

KeymgrDataODataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	248824395	248642368	0	0
T1	147933	147838	0	0
T2	212398	207805	0	0
T3	190036	189907	0	0
T4	178672	178663	0	0
T5	297393	297258	0	0
T6	113827	113812	0	0
T7	98571	98454	0	0
T8	159075	158999	0	0
T9	189937	189863	0	0
T10	362843	362651	0	0

KeymgrDataOValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	248824395	248642368	0	0
T1	147933	147838	0	0
T2	212398	207805	0	0
T3	190036	189907	0	0
T4	178672	178663	0	0
T5	297393	297258	0	0
T6	113827	113812	0	0
T7	98571	98454	0	0
T8	159075	158999	0	0
T9	189937	189863	0	0
T10	362843	362651	0	0

KeymgrValidChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	248824395	0	0	332

KmacDataODataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	248824395	150066344	0	0
T1	147933	147634	0	0
T2	212398	206211	0	0
T3	190036	189776	0	0
T4	178672	73816	0	0
T5	297393	295673	0	0
T6	113827	539860	0	0
T7	98571	98322	0	0
T8	159075	158675	0	0
T9	189937	189000	0	0
T10	362843	361099	0	0

KmacDataODataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	248824395	248642368	0	0
T1	147933	147838	0	0
T2	212398	207805	0	0
T3	190036	189907	0	0
T4	178672	178663	0	0
T5	297393	297258	0	0
T6	113827	113812	0	0
T7	98571	98454	0	0
T8	159075	158999	0	0
T9	189937	189863	0	0
T10	362843	362651	0	0

KmacDataOValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	248824395	248642368	0	0
T1	147933	147838	0	0
T2	212398	207805	0	0
T3	190036	189907	0	0
T4	178672	178663	0	0
T5	297393	297258	0	0
T6	113827	113812	0	0
T7	98571	98454	0	0
T8	159075	158999	0	0
T9	189937	189863	0	0
T10	362843	362651	0	0

PwrmgrDataChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	248824395	0	0	332

PwrmgrDataOKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	248824395	248642368	0	0
T1	147933	147838	0	0
T2	212398	207805	0	0
T3	190036	189907	0	0
T4	178672	178663	0	0
T5	297393	297258	0	0
T6	113827	113812	0	0
T7	98571	98454	0	0
T8	159075	158999	0	0
T9	189937	189863	0	0
T10	362843	362651	0	0

RegsTlOAReadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	248824395	248642368	0	0
T1	147933	147838	0	0
T2	212398	207805	0	0
T3	190036	189907	0	0
T4	178672	178663	0	0
T5	297393	297258	0	0
T6	113827	113812	0	0
T7	98571	98454	0	0
T8	159075	158999	0	0
T9	189937	189863	0	0
T10	362843	362651	0	0

RegsTlODDataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	248824395	14786257	0	0
T1	147933	31	0	0
T2	212398	20	0	0
T3	190036	1	0	0
T4	178672	457517	0	0
T5	297393	32	0	0
T6	113827	52842	0	0
T7	98571	3	0	0
T8	159075	0	0	0
T9	189937	0	0	0
T10	362843	83	0	0
T15	0	32	0	0
T20	0	1	0	0

RegsTlODDataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	248824395	248642368	0	0
T1	147933	147838	0	0
T2	212398	207805	0	0
T3	190036	189907	0	0
T4	178672	178663	0	0
T5	297393	297258	0	0
T6	113827	113812	0	0
T7	98571	98454	0	0
T8	159075	158999	0	0
T9	189937	189863	0	0
T10	362843	362651	0	0

RegsTlODValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	248824395	248642368	0	0
T1	147933	147838	0	0
T2	212398	207805	0	0
T3	190036	189907	0	0
T4	178672	178663	0	0
T5	297393	297258	0	0
T6	113827	113812	0	0
T7	98571	98454	0	0
T8	159075	158999	0	0
T9	189937	189863	0	0
T10	362843	362651	0	0

RomTlOAReadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	248824395	248642368	0	0
T1	147933	147838	0	0
T2	212398	207805	0	0
T3	190036	189907	0	0
T4	178672	178663	0	0
T5	297393	297258	0	0
T6	113827	113812	0	0
T7	98571	98454	0	0
T8	159075	158999	0	0
T9	189937	189863	0	0
T10	362843	362651	0	0

RomTlODDataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	248824395	21837727	0	0
T4	178672	617468	0	0
T5	297393	86	0	0
T6	113827	62678	0	0
T8	159075	0	0	0
T9	189937	57	0	0
T10	362843	323	0	0
T15	11733	363	0	0
T16	177364	298	0	0
T17	346307	244	0	0
T18	0	40	0	0
T19	0	329	0	0
T20	392149	0	0	0

RomTlODDataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	248824395	248642368	0	0
T1	147933	147838	0	0
T2	212398	207805	0	0
T3	190036	189907	0	0
T4	178672	178663	0	0
T5	297393	297258	0	0
T6	113827	113812	0	0
T7	98571	98454	0	0
T8	159075	158999	0	0
T9	189937	189863	0	0
T10	362843	362651	0	0

RomTlODValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	248824395	248642368	0	0
T1	147933	147838	0	0
T2	212398	207805	0	0
T3	190036	189907	0	0
T4	178672	178663	0	0
T5	297393	297258	0	0
T6	113827	113812	0	0
T7	98571	98454	0	0
T8	159075	158999	0	0
T9	189937	189863	0	0
T10	362843	362651	0	0

StabilityChkKmac_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	248824395	150063719	0	0
T1	147933	147633	0	0
T2	212398	206150	0	0
T3	190036	189774	0	0
T4	178672	73810	0	0
T5	297393	295671	0	0
T6	113827	539854	0	0
T7	98571	98320	0	0
T8	159075	158674	0	0
T9	189937	188999	0	0
T10	362843	361097	0	0

StabilityChkkeymgr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	248824395	98440927	0	0
T1	147933	136	0	0
T2	212398	16	0	0
T3	190036	60	0	0
T4	178672	171241	0	0
T5	297393	1400	0	0
T6	113827	598120	0	0
T7	98571	52	0	0
T8	159075	288	0	0
T9	189937	838	0	0
T10	362843	1481	0	0

TlAccessChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	248824395	150200126	0	0
T1	147933	147701	0	0
T2	212398	207774	0	0
T3	190036	189846	0	0
T4	178672	74212	0	0
T5	297393	295856	0	0
T6	113827	540004	0	0
T7	98571	98401	0	0
T8	159075	158710	0	0
T9	189937	189024	0	0
T10	362843	361168	0	0

gen_asserts_with_scrambling.FpvSecCmCheckerFsmAlert_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	248824395	80	0	0
T2	212398	20	0	0
T3	190036	0	0	0
T4	178672	0	0	0
T5	297393	0	0	0
T6	113827	0	0	0
T7	98571	0	0	0
T8	159075	0	0	0
T9	189937	0	0	0
T10	362843	0	0	0
T20	392149	0	0	0
T40	0	10	0	0
T41	0	20	0	0
T50	0	20	0	0
T51	0	10	0	0

gen_asserts_with_scrambling.FpvSecCmCompareAddrCtrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	248824395	0	0	0

gen_asserts_with_scrambling.FpvSecCmCompareFsmAlert_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	248824395	561	0	0
T2	212398	20	0	0
T3	190036	0	0	0
T4	178672	0	0	0
T5	297393	0	0	0
T6	113827	0	0	0
T7	98571	0	0	0
T8	159075	0	0	0
T9	189937	0	0	0
T10	362843	0	0	0
T18	0	15	0	0
T20	392149	0	0	0
T27	0	15	0	0
T28	0	5	0	0
T29	0	5	0	0
T52	0	10	0	0
T53	0	10	0	0
T54	0	5	0	0
T55	0	6	0	0
T56	0	20	0	0

gen_fsm_scramble_enabled_asserts.BusLocalEscChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	248824395	0	0	0