Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

2418588

1

T1

62

T2

57

T3

54

full_word

1034662

1

T1

6

T2

4

T3

8

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	3452950	1			T1	68		T2	61		T3	62
auto[TlIntgErrCmd]	106	1			T58	3		T59	8		T60	10
auto[TlIntgErrData]	93	1			T58	2		T59	5		T60	4
auto[TlIntgErrBoth]	101	1			T58	5		T59	7		T60	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

428591

1

T1

68

T2

61

T3

62

auto[1]

3024659

1

T14

180842

T15

105997

T16

220460

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	189324	1			T1	62		T2	57		T3	54
auto[TlIntgErrNone]	partial	auto[1]	2228987	1			T14	132131		T15	79420		T16	162449
auto[TlIntgErrNone]	full_word	auto[0]	239138	1			T1	6		T2	4		T3	8
auto[TlIntgErrNone]	full_word	auto[1]	795501	1			T14	48711		T15	26577		T16	58011
auto[TlIntgErrCmd]	partial	auto[0]	45	1			T58	2		T59	7		T60	6
auto[TlIntgErrCmd]	partial	auto[1]	55	1			T58	1		T60	3		T109	2
auto[TlIntgErrCmd]	full_word	auto[0]	1	1			T111	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T59	1		T60	1		T112	1
auto[TlIntgErrData]	partial	auto[0]	45	1			T58	1		T60	1		T109	1
auto[TlIntgErrData]	partial	auto[1]	38	1			T59	4		T60	3		T109	3
auto[TlIntgErrData]	full_word	auto[0]	3	1			T110	1		T113	1		T114	1
auto[TlIntgErrData]	full_word	auto[1]	7	1			T58	1		T59	1		T113	1
auto[TlIntgErrBoth]	partial	auto[0]	33	1			T59	1		T60	2		T109	3
auto[TlIntgErrBoth]	partial	auto[1]	61	1			T58	5		T59	5		T60	4
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T112	1		T115	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T59	1		T105	1		T115	1