Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3603690

1

T1

257

T2

156

T3

160

full_word

1573813

1

T1

24

T2

18

T3

16

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	5177223	1			T1	281		T2	174		T3	176
auto[TlIntgErrCmd]	86	1			T59	3		T60	3		T61	8
auto[TlIntgErrData]	91	1			T59	7		T60	5		T61	4
auto[TlIntgErrBoth]	103	1			T59	10		T60	2		T61	8

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

630076

1

T1

281

T2

174

T3

176

auto[1]

4547427

1

T9

61083

T13

122281

T14

113843

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	266528	1			T1	257		T2	156		T3	160
auto[TlIntgErrNone]	partial	auto[1]	3336902	1			T9	44542		T13	87276		T14	84847
auto[TlIntgErrNone]	full_word	auto[0]	363422	1			T1	24		T2	18		T3	16
auto[TlIntgErrNone]	full_word	auto[1]	1210371	1			T9	16541		T13	35005		T14	28996
auto[TlIntgErrCmd]	partial	auto[0]	29	1			T59	1		T127	1		T130	1
auto[TlIntgErrCmd]	partial	auto[1]	52	1			T59	2		T60	3		T61	7
auto[TlIntgErrCmd]	full_word	auto[0]	1	1			T128	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T61	1		T135	1		T129	1
auto[TlIntgErrData]	partial	auto[0]	51	1			T59	4		T60	4		T61	2
auto[TlIntgErrData]	partial	auto[1]	36	1			T59	3		T61	2		T130	2
auto[TlIntgErrData]	full_word	auto[0]	1	1			T127	1		-	-		-	-
auto[TlIntgErrData]	full_word	auto[1]	3	1			T60	1		T128	1		T136	1
auto[TlIntgErrBoth]	partial	auto[0]	41	1			T59	3		T61	2		T127	2
auto[TlIntgErrBoth]	partial	auto[1]	51	1			T59	5		T60	2		T61	6
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T134	1		T137	1		T138	1
auto[TlIntgErrBoth]	full_word	auto[1]	8	1			T59	2		T130	1		T129	1