Unified Coverage Report :: Module :: rom_ctrl

Module : rom_ctrl

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.98	100.00	98.28	97.33		100.00	79.31

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	94.98	100.00	98.28	97.33		100.00	79.31

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.98	100.00	98.28	97.33		100.00	79.31

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.33	97.04	92.65	97.88	100.00	98.37	98.04

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_alert_tx[0].u_alert_sender	100.00			100.00
gen_fsm_scramble_enabled.u_checker_fsm	95.92	100.00	96.30	90.00	100.00	98.31	90.91
gen_rom_scramble_enabled.u_rom	97.06	88.24		100.00		100.00	100.00
regs_tlul_assert_device	100.00	100.00				100.00	100.00
rom_ctrl_regs_csr_assert	100.00						100.00
rom_tlul_assert_device	99.30	100.00				100.00	97.90
u_mux	95.24	100.00	85.71			100.00
u_reg_regs	99.72	99.41	99.21	100.00		100.00	100.00
u_rom_top	100.00	100.00				100.00	100.00
u_tl_adapter_rom	93.77	91.56	83.06	99.07		95.18	100.00
u_tl_rom_h2d_buf	100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rom_ctrl

	Line No.	Total	Covered	Percent
TOTAL		65	65	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	123	1	1	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	221	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	322	1	1	100.00
CONT_ASSIGN	423	1	1	100.00
CONT_ASSIGN	423	1	1	100.00
CONT_ASSIGN	423	1	1	100.00
CONT_ASSIGN	423	1	1	100.00
CONT_ASSIGN	423	1	1	100.00
CONT_ASSIGN	423	1	1	100.00
CONT_ASSIGN	423	1	1	100.00
CONT_ASSIGN	423	1	1	100.00
CONT_ASSIGN	424	1	1	100.00
CONT_ASSIGN	424	1	1	100.00
CONT_ASSIGN	424	1	1	100.00
CONT_ASSIGN	424	1	1	100.00
CONT_ASSIGN	424	1	1	100.00
CONT_ASSIGN	424	1	1	100.00
CONT_ASSIGN	424	1	1	100.00
CONT_ASSIGN	424	1	1	100.00
CONT_ASSIGN	426	1	1	100.00
CONT_ASSIGN	426	1	1	100.00
CONT_ASSIGN	426	1	1	100.00
CONT_ASSIGN	426	1	1	100.00
CONT_ASSIGN	426	1	1	100.00
CONT_ASSIGN	426	1	1	100.00
CONT_ASSIGN	426	1	1	100.00
CONT_ASSIGN	426	1	1	100.00
CONT_ASSIGN	427	1	1	100.00
CONT_ASSIGN	427	1	1	100.00
CONT_ASSIGN	427	1	1	100.00
CONT_ASSIGN	427	1	1	100.00
CONT_ASSIGN	427	1	1	100.00
CONT_ASSIGN	427	1	1	100.00
CONT_ASSIGN	427	1	1	100.00
CONT_ASSIGN	427	1	1	100.00
CONT_ASSIGN	429	1	1	100.00
CONT_ASSIGN	429	1	1	100.00
CONT_ASSIGN	429	1	1	100.00
CONT_ASSIGN	429	1	1	100.00
CONT_ASSIGN	429	1	1	100.00
CONT_ASSIGN	429	1	1	100.00
CONT_ASSIGN	429	1	1	100.00
CONT_ASSIGN	429	1	1	100.00
CONT_ASSIGN	430	1	1	100.00
CONT_ASSIGN	430	1	1	100.00
CONT_ASSIGN	430	1	1	100.00
CONT_ASSIGN	430	1	1	100.00
CONT_ASSIGN	430	1	1	100.00
CONT_ASSIGN	430	1	1	100.00
CONT_ASSIGN	430	1	1	100.00
CONT_ASSIGN	430	1	1	100.00
CONT_ASSIGN	434	1	1	100.00
CONT_ASSIGN	436	1	1	100.00
CONT_ASSIGN	439	1	1	100.00
CONT_ASSIGN	440	1	1	100.00
CONT_ASSIGN	441	1	1	100.00
CONT_ASSIGN	442	1	1	100.00
CONT_ASSIGN	447	1	1	100.00
CONT_ASSIGN	451	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv' or '../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
118	1	1
123	1	1
124	1	1
125	1	1
126	1	1
129	1	1
221	1	1
267	1	1
322	1	1
423	8	8
424	8	8
426	8	8
427	8	8
429	8	8
430	8	8
434	1	1
436	1	1
439	1	1
440	1	1
441	1	1
442	1	1
447	1	1
451	1	1

---

Cond Coverage for Module : rom_ctrl

	Total	Covered	Percent
Conditions	58	57	98.28
Logical	58	57	98.28
Non-Logical	0	0
Event	0	0

 LINE       221
 EXPRESSION (tl_rom_h2d_upstream.a_valid ? tl_rom_h2d_upstream.a_address[2+:RomIndexWidth] : '0)
             -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       267
 EXPRESSION (bus_rom_rvalid_raw & ((!internal_alert)))
             ---------1--------   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T15,T11
1	1	Covered	T1,T2,T3

 LINE       427
 EXPRESSION (exp_digest_de && (0[2:0] == exp_digest_idx))
             ------1------    -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       427
 SUB-EXPRESSION (0[2:0] == exp_digest_idx)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       427
 EXPRESSION (exp_digest_de && (1[2:0] == exp_digest_idx))
             ------1------    -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       427
 SUB-EXPRESSION (1[2:0] == exp_digest_idx)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       427
 EXPRESSION (exp_digest_de && (2[2:0] == exp_digest_idx))
             ------1------    -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       427
 SUB-EXPRESSION (2[2:0] == exp_digest_idx)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       427
 EXPRESSION (exp_digest_de && (3[2:0] == exp_digest_idx))
             ------1------    -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       427
 SUB-EXPRESSION (3[2:0] == exp_digest_idx)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       427
 EXPRESSION (exp_digest_de && (4[2:0] == exp_digest_idx))
             ------1------    -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       427
 SUB-EXPRESSION (4[2:0] == exp_digest_idx)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       427
 EXPRESSION (exp_digest_de && (5[2:0] == exp_digest_idx))
             ------1------    -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       427
 SUB-EXPRESSION (5[2:0] == exp_digest_idx)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       427
 EXPRESSION (exp_digest_de && (6[2:0] == exp_digest_idx))
             ------1------    -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       427
 SUB-EXPRESSION (6[2:0] == exp_digest_idx)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       427
 EXPRESSION (exp_digest_de && (7[2:0] == exp_digest_idx))
             ------1------    -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       427
 SUB-EXPRESSION (7[2:0] == exp_digest_idx)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       434
 EXPRESSION (rom_reg_integrity_error | rom_integrity_error | reg_integrity_error)
             -----------1-----------   ---------2---------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T34,T35,T36
0	1	0	Not Covered
1	0	0	Unreachable

 LINE       436
 EXPRESSION (checker_alert | mux_alert)
             ------1------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T15,T11
1	0	Covered	T5,T6,T8

 LINE       447
 EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
             ---------1---------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T7,T37,T38
1	0	Covered	T2,T3,T4
1	1	Covered	T7,T37,T12

 LINE       451
 EXPRESSION (bus_integrity_error | checker_alert | mux_alert)
             ---------1---------   ------2------   ----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T6,T15,T11
0	1	0	Covered	T5,T6,T8
1	0	0	Covered	T34,T35,T36

---

Toggle Coverage for Module : rom_ctrl

	Total	Covered	Percent
Totals	61	56	91.80
Total Bits	2882	2805	97.33
Total Bits 0->1	1441	1402	97.29
Total Bits 1->0	1441	1403	97.36

Ports	61	56	91.80
Port Bits	2882	2805	97.33
Port Bits 0->1	1441	1402	97.29
Port Bits 1->0	1441	1403	97.36

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
rom_cfg_i.cfg[3:0]	No	No		No		INPUT
rom_cfg_i.cfg_en	No	No		No		INPUT
rom_tl_i.d_ready	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
rom_tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rom_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rom_tl_i.a_user.instr_type[3:0]	Yes	Yes	T3,T5,T9	Yes	T3,T9,T11	INPUT
rom_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
rom_tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rom_tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rom_tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rom_tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rom_tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rom_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
rom_tl_i.a_opcode[2:0]	Yes	Yes	T3,T9,T11	Yes	T3,T5,T9	INPUT
rom_tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rom_tl_o.a_ready	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	OUTPUT
rom_tl_o.d_error	Yes	Yes	T9,T13,T14	Yes	T9,T13,T14	OUTPUT
rom_tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
rom_tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
rom_tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
rom_tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
rom_tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
rom_tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
rom_tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
rom_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
rom_tl_o.d_opcode[0]	Yes	Yes	*T9,*T13,*T14	Yes	T9,T13,T14	OUTPUT
rom_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
rom_tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
regs_tl_i.d_ready	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
regs_tl_i.a_user.data_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
regs_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
regs_tl_i.a_user.instr_type[3:0]	Yes	Yes	T6,T9,T15	Yes	T6,T9,T15	INPUT
regs_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_data[31:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
regs_tl_i.a_mask[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
regs_tl_i.a_address[31:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
regs_tl_i.a_source[7:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
regs_tl_i.a_size[1:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
regs_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_opcode[2:0]	Yes	Yes	T6,T7,T9	Yes	T6,T7,T9	INPUT
regs_tl_i.a_valid	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
regs_tl_o.a_ready	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
regs_tl_o.d_error	Yes	Yes	T9,T13,T14	Yes	T9,T13,T14	OUTPUT
regs_tl_o.d_user.data_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
regs_tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T2,*T3,*T4	Yes	T2,T3,T4	OUTPUT
regs_tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_data[31:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
regs_tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_source[7:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
regs_tl_o.d_size[1:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
regs_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_opcode[0]	Yes	Yes	*T2,*T3,*T4	Yes	T2,T3,T4	OUTPUT
regs_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_valid	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
pwrmgr_data_o.good[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
pwrmgr_data_o.done[3:0]	Yes	Yes	T1,T2,T3	Yes	T2,T3,T4	OUTPUT
keymgr_data_o.valid	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	OUTPUT
keymgr_data_o.data[255:0]	Yes	Yes	T2,T3,T5	Yes	T2,T3,T4	OUTPUT
kmac_data_i.error	No	Yes	T5,T8,T28	No		INPUT
kmac_data_i.digest_share1[383:0]	Yes	Yes	T2,T6,T15	Yes	T2,T3,T6	INPUT
kmac_data_i.digest_share0[383:0]	Yes	Yes	T4,T6,T8	Yes	T2,T6,T15	INPUT
kmac_data_i.done	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
kmac_data_i.ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
kmac_data_o.last	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
kmac_data_o.strb[7:0]	No	No		No		OUTPUT
kmac_data_o.data[38:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
kmac_data_o.data[63:39]	No	No		No		OUTPUT
kmac_data_o.valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Module : rom_ctrl

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
TERNARY	221	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv' or '../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	221	(tl_rom_h2d_upstream.a_valid) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : rom_ctrl

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	29	29	100.00	23	79.31
Cover properties	0	0		0
Cover sequences	0	0		0
Total	29	29	100.00	23	79.31

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxOKnown_A	174170081	174034956	0	0
BusRomIndicesMatch_A	174159537	174028425	0	0
FpvSecCmFifoRptrCheck_A	174170081	0	0	0
FpvSecCmFifoWptrCheck_A	174170081	0	0	0
FpvSecCmRegWeOnehotCheck_A	174170081	80	0	0
KeymgrDataODataKnown_A	174170081	69719287	0	0
KeymgrDataODataKnown_AKnownEnable	174170081	174034956	0	0
KeymgrDataOValidKnown_A	174170081	174034956	0	0
KeymgrValidChk_A	174170081	0	0	302
KmacDataODataKnown_A	174170081	104216896	0	0
KmacDataODataKnown_AKnownEnable	174170081	174034956	0	0
KmacDataOValidKnown_A	174170081	174034956	0	0
PwrmgrDataChk_A	174170081	0	0	302
PwrmgrDataOKnown_A	174170081	174034956	0	0
RegsTlOAReadyKnown_A	174170081	174034956	0	0
RegsTlODDataKnown_A	174170081	10272287	0	0
RegsTlODDataKnown_AKnownEnable	174170081	174034956	0	0
RegsTlODValidKnown_A	174170081	174034956	0	0
RomTlOAReadyKnown_A	174170081	174034956	0	0
RomTlODDataKnown_A	174170081	13854598	0	0
RomTlODDataKnown_AKnownEnable	174170081	174034956	0	0
RomTlODValidKnown_A	174170081	174034956	0	0
StabilityChkKmac_A	174170081	104215006	0	0
StabilityChkkeymgr_A	174170081	69718292	0	0
TlAccessChk_A	174170081	104315669	0	0
gen_asserts_with_scrambling.FpvSecCmCheckerFsmAlert_A	174170081	80	0	0
gen_asserts_with_scrambling.FpvSecCmCompareAddrCtrCheck_A	174170081	0	0	0
gen_asserts_with_scrambling.FpvSecCmCompareFsmAlert_A	174170081	367	0	0
gen_fsm_scramble_enabled_asserts.BusLocalEscChk_A	174170081	0	0	0

AlertTxOKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	174170081	174034956	0	0
T1	116754	116701	0	0
T2	211087	210661	0	0
T3	590840	590548	0	0
T4	43153	42984	0	0
T5	287350	287226	0	0
T6	209701	209405	0	0
T7	20811	20759	0	0
T8	205167	205021	0	0
T9	141812	141804	0	0
T10	189425	189339	0	0

BusRomIndicesMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	174159537	174028425	0	0
T1	116754	116701	0	0
T2	211087	210661	0	0
T3	590840	590548	0	0
T4	43153	42984	0	0
T5	287350	287226	0	0
T6	209675	209399	0	0
T7	20811	20759	0	0
T8	205167	205021	0	0
T9	141812	141804	0	0
T10	189425	189339	0	0

FpvSecCmFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	174170081	0	0	0

FpvSecCmFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	174170081	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	174170081	80	0	0
T23	393943	0	0	0
T26	100376	0	0	0
T34	174954	20	0	0
T35	0	20	0	0
T36	0	10	0	0
T39	0	20	0	0
T40	0	10	0	0
T41	193190	0	0	0
T42	9068	0	0	0
T43	285196	0	0	0
T44	100694	0	0	0
T45	911439	0	0	0
T46	366657	0	0	0
T47	82015	0	0	0

KeymgrDataODataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	174170081	69719287	0	0
T1	116754	1487	0	0
T2	211087	4586	0	0
T3	590840	2921	0	0
T4	43153	1849	0	0
T5	287350	284	0	0
T6	209701	5467	0	0
T7	20811	277	0	0
T8	205167	137	0	0
T9	141812	953507	0	0
T10	189425	1296	0	0

KeymgrDataODataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	174170081	174034956	0	0
T1	116754	116701	0	0
T2	211087	210661	0	0
T3	590840	590548	0	0
T4	43153	42984	0	0
T5	287350	287226	0	0
T6	209701	209405	0	0
T7	20811	20759	0	0
T8	205167	205021	0	0
T9	141812	141804	0	0
T10	189425	189339	0	0

KeymgrDataOValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	174170081	174034956	0	0
T1	116754	116701	0	0
T2	211087	210661	0	0
T3	590840	590548	0	0
T4	43153	42984	0	0
T5	287350	287226	0	0
T6	209701	209405	0	0
T7	20811	20759	0	0
T8	205167	205021	0	0
T9	141812	141804	0	0
T10	189425	189339	0	0

KeymgrValidChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	174170081	0	0	302

KmacDataODataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	174170081	104216896	0	0
T1	116754	115193	0	0
T2	211087	205725	0	0
T3	590840	587370	0	0
T4	43153	41055	0	0
T5	287350	286753	0	0
T6	209701	208662	0	0
T7	20811	20406	0	0
T8	205167	204670	0	0
T9	141812	464311	0	0
T10	189425	188021	0	0

KmacDataODataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	174170081	174034956	0	0
T1	116754	116701	0	0
T2	211087	210661	0	0
T3	590840	590548	0	0
T4	43153	42984	0	0
T5	287350	287226	0	0
T6	209701	209405	0	0
T7	20811	20759	0	0
T8	205167	205021	0	0
T9	141812	141804	0	0
T10	189425	189339	0	0

KmacDataOValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	174170081	174034956	0	0
T1	116754	116701	0	0
T2	211087	210661	0	0
T3	590840	590548	0	0
T4	43153	42984	0	0
T5	287350	287226	0	0
T6	209701	209405	0	0
T7	20811	20759	0	0
T8	205167	205021	0	0
T9	141812	141804	0	0
T10	189425	189339	0	0

PwrmgrDataChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	174170081	0	0	302

PwrmgrDataOKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	174170081	174034956	0	0
T1	116754	116701	0	0
T2	211087	210661	0	0
T3	590840	590548	0	0
T4	43153	42984	0	0
T5	287350	287226	0	0
T6	209701	209405	0	0
T7	20811	20759	0	0
T8	205167	205021	0	0
T9	141812	141804	0	0
T10	189425	189339	0	0

RegsTlOAReadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	174170081	174034956	0	0
T1	116754	116701	0	0
T2	211087	210661	0	0
T3	590840	590548	0	0
T4	43153	42984	0	0
T5	287350	287226	0	0
T6	209701	209405	0	0
T7	20811	20759	0	0
T8	205167	205021	0	0
T9	141812	141804	0	0
T10	189425	189339	0	0

RegsTlODDataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	174170081	10272287	0	0
T2	211087	453	0	0
T3	590840	64	0	0
T4	43153	32	0	0
T5	287350	1	0	0
T6	209701	91	0	0
T7	20811	5	0	0
T8	205167	6	0	0
T9	141812	55460	0	0
T10	189425	0	0	0
T15	0	18	0	0
T21	9298	0	0	0
T37	0	32	0	0

RegsTlODDataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	174170081	174034956	0	0
T1	116754	116701	0	0
T2	211087	210661	0	0
T3	590840	590548	0	0
T4	43153	42984	0	0
T5	287350	287226	0	0
T6	209701	209405	0	0
T7	20811	20759	0	0
T8	205167	205021	0	0
T9	141812	141804	0	0
T10	189425	189339	0	0

RegsTlODValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	174170081	174034956	0	0
T1	116754	116701	0	0
T2	211087	210661	0	0
T3	590840	590548	0	0
T4	43153	42984	0	0
T5	287350	287226	0	0
T6	209701	209405	0	0
T7	20811	20759	0	0
T8	205167	205021	0	0
T9	141812	141804	0	0
T10	189425	189339	0	0

RomTlOAReadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	174170081	174034956	0	0
T1	116754	116701	0	0
T2	211087	210661	0	0
T3	590840	590548	0	0
T4	43153	42984	0	0
T5	287350	287226	0	0
T6	209701	209405	0	0
T7	20811	20759	0	0
T8	205167	205021	0	0
T9	141812	141804	0	0
T10	189425	189339	0	0

RomTlODDataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	174170081	13854598	0	0
T1	116754	281	0	0
T2	211087	174	0	0
T3	590840	176	0	0
T4	43153	77	0	0
T5	287350	0	0	0
T6	209701	32	0	0
T7	20811	0	0	0
T8	205167	0	0	0
T9	141812	69458	0	0
T10	189425	355	0	0
T15	0	49	0	0
T21	0	118	0	0
T22	0	405	0	0

RomTlODDataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	174170081	174034956	0	0
T1	116754	116701	0	0
T2	211087	210661	0	0
T3	590840	590548	0	0
T4	43153	42984	0	0
T5	287350	287226	0	0
T6	209701	209405	0	0
T7	20811	20759	0	0
T8	205167	205021	0	0
T9	141812	141804	0	0
T10	189425	189339	0	0

RomTlODValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	174170081	174034956	0	0
T1	116754	116701	0	0
T2	211087	210661	0	0
T3	590840	590548	0	0
T4	43153	42984	0	0
T5	287350	287226	0	0
T6	209701	209405	0	0
T7	20811	20759	0	0
T8	205167	205021	0	0
T9	141812	141804	0	0
T10	189425	189339	0	0

StabilityChkKmac_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	174170081	104215006	0	0
T1	116754	115192	0	0
T2	211087	205719	0	0
T3	590840	587366	0	0
T4	43153	41053	0	0
T5	287350	286751	0	0
T6	209701	208658	0	0
T7	20811	20405	0	0
T8	205167	204668	0	0
T9	141812	464308	0	0
T10	189425	188020	0	0

StabilityChkkeymgr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	174170081	69718292	0	0
T1	116754	1486	0	0
T2	211087	4581	0	0
T3	590840	2918	0	0
T4	43153	1847	0	0
T5	287350	283	0	0
T6	209701	5452	0	0
T7	20811	276	0	0
T8	205167	136	0	0
T9	141812	953504	0	0
T10	189425	1295	0	0

TlAccessChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	174170081	104315669	0	0
T1	116754	115214	0	0
T2	211087	206075	0	0
T3	590840	587627	0	0
T4	43153	41135	0	0
T5	287350	286942	0	0
T6	209701	208858	0	0
T7	20811	20482	0	0
T8	205167	204884	0	0
T9	141812	464540	0	0
T10	189425	188043	0	0

gen_asserts_with_scrambling.FpvSecCmCheckerFsmAlert_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	174170081	80	0	0
T23	393943	0	0	0
T26	100376	0	0	0
T34	174954	20	0	0
T35	0	20	0	0
T36	0	10	0	0
T39	0	20	0	0
T40	0	10	0	0
T41	193190	0	0	0
T42	9068	0	0	0
T43	285196	0	0	0
T44	100694	0	0	0
T45	911439	0	0	0
T46	366657	0	0	0
T47	82015	0	0	0

gen_asserts_with_scrambling.FpvSecCmCompareAddrCtrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	174170081	0	0	0

gen_asserts_with_scrambling.FpvSecCmCompareFsmAlert_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	174170081	367	0	0
T6	209701	10	0	0
T7	20811	0	0	0
T8	205167	0	0	0
T9	141812	0	0	0
T10	189425	0	0	0
T11	563968	10	0	0
T15	298001	5	0	0
T21	9298	0	0	0
T22	189900	0	0	0
T31	0	10	0	0
T34	0	20	0	0
T37	8328	0	0	0
T48	0	15	0	0
T49	0	10	0	0
T50	0	5	0	0
T51	0	10	0	0
T52	0	5	0	0

gen_fsm_scramble_enabled_asserts.BusLocalEscChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	174170081	0	0	0