Unified Coverage Report :: Module :: rom_ctrl

Module : rom_ctrl

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.98	100.00	98.28	97.33		100.00	79.31

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	94.98	100.00	98.28	97.33		100.00	79.31

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.98	100.00	98.28	97.33		100.00	79.31

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.33	97.04	92.65	97.88	100.00	98.37	98.04

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_alert_tx[0].u_alert_sender	100.00			100.00
gen_fsm_scramble_enabled.u_checker_fsm	95.92	100.00	96.30	90.00	100.00	98.31	90.91
gen_rom_scramble_enabled.u_rom	97.06	88.24		100.00		100.00	100.00
regs_tlul_assert_device	100.00	100.00				100.00	100.00
rom_ctrl_regs_csr_assert	100.00						100.00
rom_tlul_assert_device	99.30	100.00				100.00	97.90
u_mux	95.24	100.00	85.71			100.00
u_reg_regs	99.72	99.41	99.21	100.00		100.00	100.00
u_rom_top	100.00	100.00				100.00	100.00
u_tl_adapter_rom	93.77	91.56	83.06	99.07		95.18	100.00
u_tl_rom_h2d_buf	100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rom_ctrl

	Line No.	Total	Covered	Percent
TOTAL		65	65	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	123	1	1	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	221	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	322	1	1	100.00
CONT_ASSIGN	423	1	1	100.00
CONT_ASSIGN	423	1	1	100.00
CONT_ASSIGN	423	1	1	100.00
CONT_ASSIGN	423	1	1	100.00
CONT_ASSIGN	423	1	1	100.00
CONT_ASSIGN	423	1	1	100.00
CONT_ASSIGN	423	1	1	100.00
CONT_ASSIGN	423	1	1	100.00
CONT_ASSIGN	424	1	1	100.00
CONT_ASSIGN	424	1	1	100.00
CONT_ASSIGN	424	1	1	100.00
CONT_ASSIGN	424	1	1	100.00
CONT_ASSIGN	424	1	1	100.00
CONT_ASSIGN	424	1	1	100.00
CONT_ASSIGN	424	1	1	100.00
CONT_ASSIGN	424	1	1	100.00
CONT_ASSIGN	426	1	1	100.00
CONT_ASSIGN	426	1	1	100.00
CONT_ASSIGN	426	1	1	100.00
CONT_ASSIGN	426	1	1	100.00
CONT_ASSIGN	426	1	1	100.00
CONT_ASSIGN	426	1	1	100.00
CONT_ASSIGN	426	1	1	100.00
CONT_ASSIGN	426	1	1	100.00
CONT_ASSIGN	427	1	1	100.00
CONT_ASSIGN	427	1	1	100.00
CONT_ASSIGN	427	1	1	100.00
CONT_ASSIGN	427	1	1	100.00
CONT_ASSIGN	427	1	1	100.00
CONT_ASSIGN	427	1	1	100.00
CONT_ASSIGN	427	1	1	100.00
CONT_ASSIGN	427	1	1	100.00
CONT_ASSIGN	429	1	1	100.00
CONT_ASSIGN	429	1	1	100.00
CONT_ASSIGN	429	1	1	100.00
CONT_ASSIGN	429	1	1	100.00
CONT_ASSIGN	429	1	1	100.00
CONT_ASSIGN	429	1	1	100.00
CONT_ASSIGN	429	1	1	100.00
CONT_ASSIGN	429	1	1	100.00
CONT_ASSIGN	430	1	1	100.00
CONT_ASSIGN	430	1	1	100.00
CONT_ASSIGN	430	1	1	100.00
CONT_ASSIGN	430	1	1	100.00
CONT_ASSIGN	430	1	1	100.00
CONT_ASSIGN	430	1	1	100.00
CONT_ASSIGN	430	1	1	100.00
CONT_ASSIGN	430	1	1	100.00
CONT_ASSIGN	434	1	1	100.00
CONT_ASSIGN	436	1	1	100.00
CONT_ASSIGN	439	1	1	100.00
CONT_ASSIGN	440	1	1	100.00
CONT_ASSIGN	441	1	1	100.00
CONT_ASSIGN	442	1	1	100.00
CONT_ASSIGN	447	1	1	100.00
CONT_ASSIGN	451	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv' or '../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
118	1	1
123	1	1
124	1	1
125	1	1
126	1	1
129	1	1
221	1	1
267	1	1
322	1	1
423	8	8
424	8	8
426	8	8
427	8	8
429	8	8
430	8	8
434	1	1
436	1	1
439	1	1
440	1	1
441	1	1
442	1	1
447	1	1
451	1	1

---

Cond Coverage for Module : rom_ctrl

	Total	Covered	Percent
Conditions	58	57	98.28
Logical	58	57	98.28
Non-Logical	0	0
Event	0	0

 LINE       221
 EXPRESSION (tl_rom_h2d_upstream.a_valid ? tl_rom_h2d_upstream.a_address[2+:RomIndexWidth] : '0)
             -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       267
 EXPRESSION (bus_rom_rvalid_raw & ((!internal_alert)))
             ---------1--------   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T6
1	1	Covered	T1,T2,T3

 LINE       427
 EXPRESSION (exp_digest_de && (0[2:0] == exp_digest_idx))
             ------1------    -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       427
 SUB-EXPRESSION (0[2:0] == exp_digest_idx)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       427
 EXPRESSION (exp_digest_de && (1[2:0] == exp_digest_idx))
             ------1------    -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       427
 SUB-EXPRESSION (1[2:0] == exp_digest_idx)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       427
 EXPRESSION (exp_digest_de && (2[2:0] == exp_digest_idx))
             ------1------    -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       427
 SUB-EXPRESSION (2[2:0] == exp_digest_idx)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       427
 EXPRESSION (exp_digest_de && (3[2:0] == exp_digest_idx))
             ------1------    -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       427
 SUB-EXPRESSION (3[2:0] == exp_digest_idx)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       427
 EXPRESSION (exp_digest_de && (4[2:0] == exp_digest_idx))
             ------1------    -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       427
 SUB-EXPRESSION (4[2:0] == exp_digest_idx)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       427
 EXPRESSION (exp_digest_de && (5[2:0] == exp_digest_idx))
             ------1------    -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       427
 SUB-EXPRESSION (5[2:0] == exp_digest_idx)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       427
 EXPRESSION (exp_digest_de && (6[2:0] == exp_digest_idx))
             ------1------    -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       427
 SUB-EXPRESSION (6[2:0] == exp_digest_idx)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       427
 EXPRESSION (exp_digest_de && (7[2:0] == exp_digest_idx))
             ------1------    -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       427
 SUB-EXPRESSION (7[2:0] == exp_digest_idx)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       434
 EXPRESSION (rom_reg_integrity_error | rom_integrity_error | reg_integrity_error)
             -----------1-----------   ---------2---------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T4,T32,T33
0	1	0	Not Covered
1	0	0	Unreachable

 LINE       436
 EXPRESSION (checker_alert | mux_alert)
             ------1------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T3,T4

 LINE       447
 EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
             ---------1---------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T9,T10,T34
1	0	Covered	T1,T2,T3
1	1	Covered	T9,T10,T34

 LINE       451
 EXPRESSION (bus_integrity_error | checker_alert | mux_alert)
             ---------1---------   ------2------   ----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T6
0	1	0	Covered	T1,T3,T4
1	0	0	Covered	T4,T32,T33

---

Toggle Coverage for Module : rom_ctrl

	Total	Covered	Percent
Totals	61	56	91.80
Total Bits	2882	2805	97.33
Total Bits 0->1	1441	1402	97.29
Total Bits 1->0	1441	1403	97.36

Ports	61	56	91.80
Port Bits	2882	2805	97.33
Port Bits 0->1	1441	1402	97.29
Port Bits 1->0	1441	1403	97.36

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rom_cfg_i.cfg[3:0]	No	No		No		INPUT
rom_cfg_i.cfg_en	No	No		No		INPUT
rom_tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rom_tl_i.a_user.data_intg[6:0]	Yes	Yes	T2,T5,T6	Yes	T2,T5,T6	INPUT
rom_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rom_tl_i.a_user.instr_type[3:0]	Yes	Yes	T5,T6,T8	Yes	T5,T6,T9	INPUT
rom_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
rom_tl_i.a_data[31:0]	Yes	Yes	T2,T5,T6	Yes	T2,T5,T6	INPUT
rom_tl_i.a_mask[3:0]	Yes	Yes	T2,T5,T6	Yes	T2,T5,T6	INPUT
rom_tl_i.a_address[31:0]	Yes	Yes	T2,T5,T6	Yes	T2,T5,T6	INPUT
rom_tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rom_tl_i.a_size[1:0]	Yes	Yes	T2,T5,T6	Yes	T2,T5,T6	INPUT
rom_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
rom_tl_i.a_opcode[2:0]	Yes	Yes	T5,T6,T8	Yes	T5,T6,T10	INPUT
rom_tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rom_tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
rom_tl_o.d_error	Yes	Yes	T12,T13,T14	Yes	T12,T13,T14	OUTPUT
rom_tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
rom_tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
rom_tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
rom_tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
rom_tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
rom_tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
rom_tl_o.d_size[1:0]	Yes	Yes	T2,T5,T7	Yes	T2,T5,T7	OUTPUT
rom_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
rom_tl_o.d_opcode[0]	Yes	Yes	*T12,*T13,*T14	Yes	T12,T13,T14	OUTPUT
rom_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
rom_tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
regs_tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
regs_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_opcode[2:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
regs_tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
regs_tl_o.d_error	Yes	Yes	T12,T13,T14	Yes	T12,T13,T14	OUTPUT
regs_tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
regs_tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
regs_tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
regs_tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
regs_tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
regs_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
regs_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
pwrmgr_data_o.good[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
pwrmgr_data_o.done[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
keymgr_data_o.valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
keymgr_data_o.data[255:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
kmac_data_i.error	No	Yes	T8,T22,T26	No		INPUT
kmac_data_i.digest_share1[383:0]	Yes	Yes	T1,T3,T6	Yes	T1,T2,T3	INPUT
kmac_data_i.digest_share0[383:0]	Yes	Yes	T1,T2,T3	Yes	T1,T3,T6	INPUT
kmac_data_i.done	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
kmac_data_i.ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
kmac_data_o.last	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
kmac_data_o.strb[7:0]	No	No		No		OUTPUT
kmac_data_o.data[38:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
kmac_data_o.data[63:39]	No	No		No		OUTPUT
kmac_data_o.valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Module : rom_ctrl

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
TERNARY	221	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv' or '../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	221	(tl_rom_h2d_upstream.a_valid) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : rom_ctrl

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	29	29	100.00	23	79.31
Cover properties	0	0		0
Cover sequences	0	0		0
Total	29	29	100.00	23	79.31

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxOKnown_A	217756957	217587650	0	0
BusRomIndicesMatch_A	217740409	217579123	0	0
FpvSecCmFifoRptrCheck_A	217756957	0	0	0
FpvSecCmFifoWptrCheck_A	217756957	0	0	0
FpvSecCmRegWeOnehotCheck_A	217756957	60	0	0
KeymgrDataODataKnown_A	217756957	69930641	0	0
KeymgrDataODataKnown_AKnownEnable	217756957	217587650	0	0
KeymgrDataOValidKnown_A	217756957	217587650	0	0
KeymgrValidChk_A	217756957	0	0	326
KmacDataODataKnown_A	217756957	147542076	0	0
KmacDataODataKnown_AKnownEnable	217756957	217587650	0	0
KmacDataOValidKnown_A	217756957	217587650	0	0
PwrmgrDataChk_A	217756957	0	0	326
PwrmgrDataOKnown_A	217756957	217587650	0	0
RegsTlOAReadyKnown_A	217756957	217587650	0	0
RegsTlODDataKnown_A	217756957	8827372	0	0
RegsTlODDataKnown_AKnownEnable	217756957	217587650	0	0
RegsTlODValidKnown_A	217756957	217587650	0	0
RomTlOAReadyKnown_A	217756957	217587650	0	0
RomTlODDataKnown_A	217756957	12740863	0	0
RomTlODDataKnown_AKnownEnable	217756957	217587650	0	0
RomTlODValidKnown_A	217756957	217587650	0	0
StabilityChkKmac_A	217756957	147539715	0	0
StabilityChkkeymgr_A	217756957	69929436	0	0
TlAccessChk_A	217756957	147657009	0	0
gen_asserts_with_scrambling.FpvSecCmCheckerFsmAlert_A	217756957	60	0	0
gen_asserts_with_scrambling.FpvSecCmCompareAddrCtrCheck_A	217756957	0	0	0
gen_asserts_with_scrambling.FpvSecCmCompareFsmAlert_A	217756957	483	0	0
gen_fsm_scramble_enabled_asserts.BusLocalEscChk_A	217756957	0	0	0

AlertTxOKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217756957	217587650	0	0
T1	248335	244590	0	0
T2	131234	131074	0	0
T3	311093	310895	0	0
T4	79217	76914	0	0
T5	99738	99608	0	0
T6	472696	472443	0	0
T7	739777	739416	0	0
T8	378809	378680	0	0
T9	16412	16348	0	0
T10	102666	102606	0	0

BusRomIndicesMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217740409	217579123	0	0
T1	247975	244399	0	0
T2	131234	131074	0	0
T3	311072	310891	0	0
T4	79217	76914	0	0
T5	99738	99608	0	0
T6	472656	472436	0	0
T7	739777	739416	0	0
T8	378809	378680	0	0
T9	16412	16348	0	0
T10	102666	102606	0	0

FpvSecCmFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217756957	0	0	0

FpvSecCmFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217756957	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217756957	60	0	0
T4	79217	10	0	0
T5	99738	0	0	0
T6	472696	0	0	0
T7	739777	0	0	0
T8	378809	0	0	0
T9	16412	0	0	0
T10	102666	0	0	0
T11	262686	0	0	0
T21	319633	0	0	0
T32	0	10	0	0
T33	0	20	0	0
T34	152412	0	0	0
T35	0	10	0	0
T36	0	10	0	0

KeymgrDataODataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217756957	69930641	0	0
T1	248335	8494	0	0
T2	131234	644	0	0
T3	311093	12615	0	0
T4	79217	146	0	0
T5	99738	1944	0	0
T6	472696	14829	0	0
T7	739777	4248	0	0
T8	378809	289	0	0
T9	16412	7	0	0
T10	102666	134	0	0

KeymgrDataODataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	217756957	217587650	0	0
T1	248335	244590	0	0
T2	131234	131074	0	0
T3	311093	310895	0	0
T4	79217	76914	0	0
T5	99738	99608	0	0
T6	472696	472443	0	0
T7	739777	739416	0	0
T8	378809	378680	0	0
T9	16412	16348	0	0
T10	102666	102606	0	0

KeymgrDataOValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217756957	217587650	0	0
T1	248335	244590	0	0
T2	131234	131074	0	0
T3	311093	310895	0	0
T4	79217	76914	0	0
T5	99738	99608	0	0
T6	472696	472443	0	0
T7	739777	739416	0	0
T8	378809	378680	0	0
T9	16412	16348	0	0
T10	102666	102606	0	0

KeymgrValidChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217756957	0	0	326

KmacDataODataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217756957	147542076	0	0
T1	248335	234513	0	0
T2	131234	130220	0	0
T3	311093	309514	0	0
T4	79217	75423	0	0
T5	99738	97585	0	0
T6	472696	470771	0	0
T7	739777	734932	0	0
T8	378809	378286	0	0
T9	16412	16292	0	0
T10	102666	102387	0	0

KmacDataODataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	217756957	217587650	0	0
T1	248335	244590	0	0
T2	131234	131074	0	0
T3	311093	310895	0	0
T4	79217	76914	0	0
T5	99738	99608	0	0
T6	472696	472443	0	0
T7	739777	739416	0	0
T8	378809	378680	0	0
T9	16412	16348	0	0
T10	102666	102606	0	0

KmacDataOValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217756957	217587650	0	0
T1	248335	244590	0	0
T2	131234	131074	0	0
T3	311093	310895	0	0
T4	79217	76914	0	0
T5	99738	99608	0	0
T6	472696	472443	0	0
T7	739777	739416	0	0
T8	378809	378680	0	0
T9	16412	16348	0	0
T10	102666	102606	0	0

PwrmgrDataChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217756957	0	0	326

PwrmgrDataOKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217756957	217587650	0	0
T1	248335	244590	0	0
T2	131234	131074	0	0
T3	311093	310895	0	0
T4	79217	76914	0	0
T5	99738	99608	0	0
T6	472696	472443	0	0
T7	739777	739416	0	0
T8	378809	378680	0	0
T9	16412	16348	0	0
T10	102666	102606	0	0

RegsTlOAReadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217756957	217587650	0	0
T1	248335	244590	0	0
T2	131234	131074	0	0
T3	311093	310895	0	0
T4	79217	76914	0	0
T5	99738	99608	0	0
T6	472696	472443	0	0
T7	739777	739416	0	0
T8	378809	378680	0	0
T9	16412	16348	0	0
T10	102666	102606	0	0

RegsTlODDataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217756957	8827372	0	0
T1	248335	38	0	0
T2	131234	32	0	0
T3	311093	55	0	0
T4	79217	10	0	0
T5	99738	32	0	0
T6	472696	102	0	0
T7	739777	443	0	0
T8	378809	1	0	0
T9	16412	27	0	0
T10	102666	5	0	0

RegsTlODDataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	217756957	217587650	0	0
T1	248335	244590	0	0
T2	131234	131074	0	0
T3	311093	310895	0	0
T4	79217	76914	0	0
T5	99738	99608	0	0
T6	472696	472443	0	0
T7	739777	739416	0	0
T8	378809	378680	0	0
T9	16412	16348	0	0
T10	102666	102606	0	0

RegsTlODValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217756957	217587650	0	0
T1	248335	244590	0	0
T2	131234	131074	0	0
T3	311093	310895	0	0
T4	79217	76914	0	0
T5	99738	99608	0	0
T6	472696	472443	0	0
T7	739777	739416	0	0
T8	378809	378680	0	0
T9	16412	16348	0	0
T10	102666	102606	0	0

RomTlOAReadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217756957	217587650	0	0
T1	248335	244590	0	0
T2	131234	131074	0	0
T3	311093	310895	0	0
T4	79217	76914	0	0
T5	99738	99608	0	0
T6	472696	472443	0	0
T7	739777	739416	0	0
T8	378809	378680	0	0
T9	16412	16348	0	0
T10	102666	102606	0	0

RomTlODDataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217756957	12740863	0	0
T1	248335	6	0	0
T2	131234	73	0	0
T3	311093	33	0	0
T4	79217	0	0	0
T5	99738	85	0	0
T6	472696	12	0	0
T7	739777	206	0	0
T8	378809	0	0	0
T9	16412	0	0	0
T10	102666	0	0	0
T11	0	302	0	0
T12	0	149583	0	0
T18	0	263	0	0
T21	0	45	0	0

RomTlODDataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	217756957	217587650	0	0
T1	248335	244590	0	0
T2	131234	131074	0	0
T3	311093	310895	0	0
T4	79217	76914	0	0
T5	99738	99608	0	0
T6	472696	472443	0	0
T7	739777	739416	0	0
T8	378809	378680	0	0
T9	16412	16348	0	0
T10	102666	102606	0	0

RomTlODValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217756957	217587650	0	0
T1	248335	244590	0	0
T2	131234	131074	0	0
T3	311093	310895	0	0
T4	79217	76914	0	0
T5	99738	99608	0	0
T6	472696	472443	0	0
T7	739777	739416	0	0
T8	378809	378680	0	0
T9	16412	16348	0	0
T10	102666	102606	0	0

StabilityChkKmac_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217756957	147539715	0	0
T1	248335	234465	0	0
T2	131234	130218	0	0
T3	311093	309511	0	0
T4	79217	75392	0	0
T5	99738	97583	0	0
T6	472696	470767	0	0
T7	739777	734927	0	0
T8	378809	378284	0	0
T9	16412	16291	0	0
T10	102666	102386	0	0

StabilityChkkeymgr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217756957	69929436	0	0
T1	248335	8478	0	0
T2	131234	642	0	0
T3	311093	12602	0	0
T4	79217	138	0	0
T5	99738	1942	0	0
T6	472696	14811	0	0
T7	739777	4244	0	0
T8	378809	288	0	0
T9	16412	6	0	0
T10	102666	133	0	0

TlAccessChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217756957	147657009	0	0
T1	248335	236096	0	0
T2	131234	130430	0	0
T3	311093	309633	0	0
T4	79217	76768	0	0
T5	99738	97664	0	0
T6	472696	470960	0	0
T7	739777	735168	0	0
T8	378809	378391	0	0
T9	16412	16341	0	0
T10	102666	102472	0	0

gen_asserts_with_scrambling.FpvSecCmCheckerFsmAlert_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217756957	60	0	0
T4	79217	10	0	0
T5	99738	0	0	0
T6	472696	0	0	0
T7	739777	0	0	0
T8	378809	0	0	0
T9	16412	0	0	0
T10	102666	0	0	0
T11	262686	0	0	0
T21	319633	0	0	0
T32	0	10	0	0
T33	0	20	0	0
T34	152412	0	0	0
T35	0	10	0	0
T36	0	10	0	0

gen_asserts_with_scrambling.FpvSecCmCompareAddrCtrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217756957	0	0	0

gen_asserts_with_scrambling.FpvSecCmCompareFsmAlert_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217756957	483	0	0
T1	248335	20	0	0
T2	131234	0	0	0
T3	311093	5	0	0
T4	79217	10	0	0
T5	99738	0	0	0
T6	472696	10	0	0
T7	739777	0	0	0
T8	378809	0	0	0
T9	16412	0	0	0
T10	102666	0	0	0
T24	0	10	0	0
T29	0	15	0	0
T30	0	5	0	0
T32	0	10	0	0
T37	0	10	0	0
T38	0	5	0	0

gen_fsm_scramble_enabled_asserts.BusLocalEscChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217756957	0	0	0