Module Definition
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Module : rom_ctrl_regs_csr_assert_fpv
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rom_ctrl_csr_assert_0/rom_ctrl_regs_csr_assert_fpv.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.rom_ctrl_regs_csr_assert 100.00 100.00



Module Instance : tb.dut.rom_ctrl_regs_csr_assert

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.98 100.00 98.28 97.33 100.00 79.31 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Assert Coverage for Module : rom_ctrl_regs_csr_assert_fpv
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
TlulOOBAddrErr_A 239365840 2461452 0 0


TlulOOBAddrErr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 239365840 2461452 0 0
T12 229202 64063 0 0
T13 162332 32646 0 0
T14 0 72779 0 0
T15 0 94476 0 0
T16 0 44797 0 0
T18 329670 0 0 0
T19 149145 0 0 0
T22 16624 0 0 0
T29 284143 0 0 0
T39 0 41750 0 0
T40 0 61957 0 0
T41 0 246508 0 0
T42 0 59999 0 0
T43 0 109727 0 0
T44 151455 0 0 0
T45 45869 0 0 0
T46 139904 0 0 0
T47 66694 0 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%