Unified Coverage Report :: Module :: rom_ctrl

Module : rom_ctrl

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.98	100.00	98.28	97.33		100.00	79.31

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	94.98	100.00	98.28	97.33		100.00	79.31

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.98	100.00	98.28	97.33		100.00	79.31

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.31	97.04	92.65	97.88	100.00	98.37	97.89

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_alert_tx[0].u_alert_sender	100.00			100.00
gen_fsm_scramble_enabled.u_checker_fsm	95.92	100.00	96.30	90.00	100.00	98.31	90.91
gen_rom_scramble_enabled.u_rom	97.06	88.24		100.00		100.00	100.00
regs_tlul_assert_device	100.00	100.00				100.00	100.00
rom_ctrl_regs_csr_assert	100.00						100.00
rom_tlul_assert_device	99.18	100.00				100.00	97.55
u_mux	95.24	100.00	85.71			100.00
u_reg_regs	99.72	99.41	99.21	100.00		100.00	100.00
u_rom_top	100.00	100.00				100.00	100.00
u_tl_adapter_rom	93.77	91.56	83.06	99.07		95.18	100.00
u_tl_rom_h2d_buf	100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rom_ctrl

	Line No.	Total	Covered	Percent
TOTAL		65	65	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	123	1	1	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	221	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	322	1	1	100.00
CONT_ASSIGN	423	1	1	100.00
CONT_ASSIGN	423	1	1	100.00
CONT_ASSIGN	423	1	1	100.00
CONT_ASSIGN	423	1	1	100.00
CONT_ASSIGN	423	1	1	100.00
CONT_ASSIGN	423	1	1	100.00
CONT_ASSIGN	423	1	1	100.00
CONT_ASSIGN	423	1	1	100.00
CONT_ASSIGN	424	1	1	100.00
CONT_ASSIGN	424	1	1	100.00
CONT_ASSIGN	424	1	1	100.00
CONT_ASSIGN	424	1	1	100.00
CONT_ASSIGN	424	1	1	100.00
CONT_ASSIGN	424	1	1	100.00
CONT_ASSIGN	424	1	1	100.00
CONT_ASSIGN	424	1	1	100.00
CONT_ASSIGN	426	1	1	100.00
CONT_ASSIGN	426	1	1	100.00
CONT_ASSIGN	426	1	1	100.00
CONT_ASSIGN	426	1	1	100.00
CONT_ASSIGN	426	1	1	100.00
CONT_ASSIGN	426	1	1	100.00
CONT_ASSIGN	426	1	1	100.00
CONT_ASSIGN	426	1	1	100.00
CONT_ASSIGN	427	1	1	100.00
CONT_ASSIGN	427	1	1	100.00
CONT_ASSIGN	427	1	1	100.00
CONT_ASSIGN	427	1	1	100.00
CONT_ASSIGN	427	1	1	100.00
CONT_ASSIGN	427	1	1	100.00
CONT_ASSIGN	427	1	1	100.00
CONT_ASSIGN	427	1	1	100.00
CONT_ASSIGN	429	1	1	100.00
CONT_ASSIGN	429	1	1	100.00
CONT_ASSIGN	429	1	1	100.00
CONT_ASSIGN	429	1	1	100.00
CONT_ASSIGN	429	1	1	100.00
CONT_ASSIGN	429	1	1	100.00
CONT_ASSIGN	429	1	1	100.00
CONT_ASSIGN	429	1	1	100.00
CONT_ASSIGN	430	1	1	100.00
CONT_ASSIGN	430	1	1	100.00
CONT_ASSIGN	430	1	1	100.00
CONT_ASSIGN	430	1	1	100.00
CONT_ASSIGN	430	1	1	100.00
CONT_ASSIGN	430	1	1	100.00
CONT_ASSIGN	430	1	1	100.00
CONT_ASSIGN	430	1	1	100.00
CONT_ASSIGN	434	1	1	100.00
CONT_ASSIGN	436	1	1	100.00
CONT_ASSIGN	439	1	1	100.00
CONT_ASSIGN	440	1	1	100.00
CONT_ASSIGN	441	1	1	100.00
CONT_ASSIGN	442	1	1	100.00
CONT_ASSIGN	447	1	1	100.00
CONT_ASSIGN	451	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv' or '../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
118	1	1
123	1	1
124	1	1
125	1	1
126	1	1
129	1	1
221	1	1
267	1	1
322	1	1
423	8	8
424	8	8
426	8	8
427	8	8
429	8	8
430	8	8
434	1	1
436	1	1
439	1	1
440	1	1
441	1	1
442	1	1
447	1	1
451	1	1

---

Cond Coverage for Module : rom_ctrl

	Total	Covered	Percent
Conditions	58	57	98.28
Logical	58	57	98.28
Non-Logical	0	0
Event	0	0

 LINE       221
 EXPRESSION (tl_rom_h2d_upstream.a_valid ? tl_rom_h2d_upstream.a_address[2+:RomIndexWidth] : '0)
             -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       267
 EXPRESSION (bus_rom_rvalid_raw & ((!internal_alert)))
             ---------1--------   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T20,T26
1	1	Covered	T1,T2,T3

 LINE       427
 EXPRESSION (exp_digest_de && (0[2:0] == exp_digest_idx))
             ------1------    -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       427
 SUB-EXPRESSION (0[2:0] == exp_digest_idx)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       427
 EXPRESSION (exp_digest_de && (1[2:0] == exp_digest_idx))
             ------1------    -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       427
 SUB-EXPRESSION (1[2:0] == exp_digest_idx)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       427
 EXPRESSION (exp_digest_de && (2[2:0] == exp_digest_idx))
             ------1------    -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       427
 SUB-EXPRESSION (2[2:0] == exp_digest_idx)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       427
 EXPRESSION (exp_digest_de && (3[2:0] == exp_digest_idx))
             ------1------    -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       427
 SUB-EXPRESSION (3[2:0] == exp_digest_idx)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       427
 EXPRESSION (exp_digest_de && (4[2:0] == exp_digest_idx))
             ------1------    -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       427
 SUB-EXPRESSION (4[2:0] == exp_digest_idx)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       427
 EXPRESSION (exp_digest_de && (5[2:0] == exp_digest_idx))
             ------1------    -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       427
 SUB-EXPRESSION (5[2:0] == exp_digest_idx)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       427
 EXPRESSION (exp_digest_de && (6[2:0] == exp_digest_idx))
             ------1------    -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       427
 SUB-EXPRESSION (6[2:0] == exp_digest_idx)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       427
 EXPRESSION (exp_digest_de && (7[2:0] == exp_digest_idx))
             ------1------    -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       427
 SUB-EXPRESSION (7[2:0] == exp_digest_idx)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       434
 EXPRESSION (rom_reg_integrity_error | rom_integrity_error | reg_integrity_error)
             -----------1-----------   ---------2---------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T30,T31,T32
0	1	0	Not Covered
1	0	0	Unreachable

 LINE       436
 EXPRESSION (checker_alert | mux_alert)
             ------1------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T20,T26
1	0	Covered	T3,T22,T20

 LINE       447
 EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
             ---------1---------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T8,T33,T34
1	0	Covered	T1,T2,T3
1	1	Covered	T7,T8,T33

 LINE       451
 EXPRESSION (bus_integrity_error | checker_alert | mux_alert)
             ---------1---------   ------2------   ----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T3,T20,T26
0	1	0	Covered	T3,T22,T20
1	0	0	Covered	T30,T31,T32

---

Toggle Coverage for Module : rom_ctrl

	Total	Covered	Percent
Totals	61	56	91.80
Total Bits	2882	2805	97.33
Total Bits 0->1	1441	1402	97.29
Total Bits 1->0	1441	1403	97.36

Ports	61	56	91.80
Port Bits	2882	2805	97.33
Port Bits 0->1	1441	1402	97.29
Port Bits 1->0	1441	1403	97.36

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T3,T5,T6	Yes	T1,T2,T3	INPUT
rom_cfg_i.cfg[3:0]	No	No		No		INPUT
rom_cfg_i.cfg_en	No	No		No		INPUT
rom_tl_i.d_ready	Yes	Yes	T3,T4,T5	Yes	T1,T2,T3	INPUT
rom_tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rom_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rom_tl_i.a_user.instr_type[3:0]	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	INPUT
rom_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
rom_tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rom_tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rom_tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rom_tl_i.a_source[7:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
rom_tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rom_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
rom_tl_i.a_opcode[2:0]	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	INPUT
rom_tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rom_tl_o.a_ready	Yes	Yes	T3,T4,T5	Yes	T1,T2,T3	OUTPUT
rom_tl_o.d_error	Yes	Yes	T5,T11,T12	Yes	T5,T11,T12	OUTPUT
rom_tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
rom_tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
rom_tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
rom_tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
rom_tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
rom_tl_o.d_source[7:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
rom_tl_o.d_size[1:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
rom_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
rom_tl_o.d_opcode[0]	Yes	Yes	*T5,*T11,*T12	Yes	T5,T11,T12	OUTPUT
rom_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
rom_tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
regs_tl_i.d_ready	Yes	Yes	T3,T4,T5	Yes	T1,T2,T3	INPUT
regs_tl_i.a_user.data_intg[6:0]	Yes	Yes	T3,T4,T5	Yes	T2,T3,T4	INPUT
regs_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T3,T4,T5	INPUT
regs_tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T5,T6	Yes	T5,T6,T20	INPUT
regs_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_data[31:0]	Yes	Yes	T1,T3,T4	Yes	T2,T3,T4	INPUT
regs_tl_i.a_mask[3:0]	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	INPUT
regs_tl_i.a_address[31:0]	Yes	Yes	T2,T3,T4	Yes	T1,T3,T4	INPUT
regs_tl_i.a_source[7:0]	Yes	Yes	T2,T3,T4	Yes	T3,T4,T5	INPUT
regs_tl_i.a_size[1:0]	Yes	Yes	T1,T3,T4	Yes	T3,T4,T5	INPUT
regs_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_opcode[2:0]	Yes	Yes	T5,T6,T8	Yes	T5,T6,T8	INPUT
regs_tl_i.a_valid	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	INPUT
regs_tl_o.a_ready	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	OUTPUT
regs_tl_o.d_error	Yes	Yes	T5,T11,T12	Yes	T5,T11,T12	OUTPUT
regs_tl_o.d_user.data_intg[6:0]	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	OUTPUT
regs_tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T3,*T4,T5	Yes	T3,T4,T5	OUTPUT
regs_tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_data[31:0]	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	OUTPUT
regs_tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_source[7:0]	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	OUTPUT
regs_tl_o.d_size[1:0]	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	OUTPUT
regs_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_opcode[0]	Yes	Yes	*T3,*T5,*T9	Yes	T3,T4,T5	OUTPUT
regs_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_valid	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T3,T7,T8	Yes	T3,T7,T8	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T3,T7,T8	Yes	T3,T7,T8	OUTPUT
pwrmgr_data_o.good[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
pwrmgr_data_o.done[3:0]	Yes	Yes	T1,T2,T3	Yes	T3,T5,T9	OUTPUT
keymgr_data_o.valid	Yes	Yes	T3,T5,T9	Yes	T1,T2,T3	OUTPUT
keymgr_data_o.data[255:0]	Yes	Yes	T3,T5,T9	Yes	T3,T4,T5	OUTPUT
kmac_data_i.error	No	Yes	T22,T23,T24	No		INPUT
kmac_data_i.digest_share1[383:0]	Yes	Yes	T3,T5,T9	Yes	T3,T5,T9	INPUT
kmac_data_i.digest_share0[383:0]	Yes	Yes	T3,T5,T9	Yes	T3,T5,T9	INPUT
kmac_data_i.done	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
kmac_data_i.ready	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
kmac_data_o.last	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
kmac_data_o.strb[7:0]	No	No		No		OUTPUT
kmac_data_o.data[38:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
kmac_data_o.data[63:39]	No	No		No		OUTPUT
kmac_data_o.valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Module : rom_ctrl

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
TERNARY	221	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv' or '../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	221	(tl_rom_h2d_upstream.a_valid) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : rom_ctrl

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	29	29	100.00	23	79.31
Cover properties	0	0		0
Cover sequences	0	0		0
Total	29	29	100.00	23	79.31

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxOKnown_A	197485304	197307635	0	0
BusRomIndicesMatch_A	197472801	197301651	0	0
FpvSecCmFifoRptrCheck_A	197485304	0	0	0
FpvSecCmFifoWptrCheck_A	197485304	0	0	0
FpvSecCmRegWeOnehotCheck_A	197485304	90	0	0
KeymgrDataODataKnown_A	197485304	69667870	0	0
KeymgrDataODataKnown_AKnownEnable	197485304	197307635	0	0
KeymgrDataOValidKnown_A	197485304	197307635	0	0
KeymgrValidChk_A	197485304	0	0	324
KmacDataODataKnown_A	197485304	127515222	0	0
KmacDataODataKnown_AKnownEnable	197485304	197307635	0	0
KmacDataOValidKnown_A	197485304	197307635	0	0
PwrmgrDataChk_A	197485304	0	0	324
PwrmgrDataOKnown_A	197485304	197307635	0	0
RegsTlOAReadyKnown_A	197485304	197307635	0	0
RegsTlODDataKnown_A	197485304	7485386	0	0
RegsTlODDataKnown_AKnownEnable	197485304	197307635	0	0
RegsTlODValidKnown_A	197485304	197307635	0	0
RomTlOAReadyKnown_A	197485304	197307635	0	0
RomTlODDataKnown_A	197485304	16563616	0	0
RomTlODDataKnown_AKnownEnable	197485304	197307635	0	0
RomTlODValidKnown_A	197485304	197307635	0	0
StabilityChkKmac_A	197485304	127512767	0	0
StabilityChkkeymgr_A	197485304	69666688	0	0
TlAccessChk_A	197485304	127639765	0	0
gen_asserts_with_scrambling.FpvSecCmCheckerFsmAlert_A	197485304	90	0	0
gen_asserts_with_scrambling.FpvSecCmCompareAddrCtrCheck_A	197485304	0	0	0
gen_asserts_with_scrambling.FpvSecCmCompareFsmAlert_A	197485304	533	0	0
gen_fsm_scramble_enabled_asserts.BusLocalEscChk_A	197485304	0	0	0

AlertTxOKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197485304	197307635	0	0
T1	9327	9264	0	0
T2	111284	111230	0	0
T3	460412	457752	0	0
T4	147834	147735	0	0
T5	211541	211529	0	0
T6	11744	11430	0	0
T7	119447	119377	0	0
T8	208128	208053	0	0
T9	28401	27916	0	0
T10	334921	334789	0	0

BusRomIndicesMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197472801	197301651	0	0
T1	9327	9264	0	0
T2	111284	111230	0	0
T3	460300	457733	0	0
T4	147834	147735	0	0
T5	211541	211529	0	0
T6	11744	11430	0	0
T7	119447	119377	0	0
T8	208128	208053	0	0
T9	28401	27916	0	0
T10	334921	334789	0	0

FpvSecCmFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197485304	0	0	0

FpvSecCmFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197485304	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197485304	90	0	0
T24	309997	0	0	0
T27	989759	0	0	0
T30	217233	20	0	0
T31	0	20	0	0
T32	0	10	0	0
T35	0	20	0	0
T36	0	20	0	0
T37	17558	0	0	0
T38	42957	0	0	0
T39	135451	0	0	0
T40	134714	0	0	0
T41	582575	0	0	0
T42	74454	0	0	0
T43	20543	0	0	0

KeymgrDataODataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197485304	69667870	0	0
T1	9327	1059	0	0
T2	111284	1106	0	0
T3	460412	26504	0	0
T4	147834	4139	0	0
T5	211541	156342	0	0
T6	11744	2194	0	0
T7	119447	61	0	0
T8	208128	64	0	0
T9	28401	1715	0	0
T10	334921	746	0	0

KeymgrDataODataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	197485304	197307635	0	0
T1	9327	9264	0	0
T2	111284	111230	0	0
T3	460412	457752	0	0
T4	147834	147735	0	0
T5	211541	211529	0	0
T6	11744	11430	0	0
T7	119447	119377	0	0
T8	208128	208053	0	0
T9	28401	27916	0	0
T10	334921	334789	0	0

KeymgrDataOValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197485304	197307635	0	0
T1	9327	9264	0	0
T2	111284	111230	0	0
T3	460412	457752	0	0
T4	147834	147735	0	0
T5	211541	211529	0	0
T6	11744	11430	0	0
T7	119447	119377	0	0
T8	208128	208053	0	0
T9	28401	27916	0	0
T10	334921	334789	0	0

KeymgrValidChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197485304	0	0	324

KmacDataODataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197485304	127515222	0	0
T1	9327	8184	0	0
T2	111284	110084	0	0
T3	460412	429341	0	0
T4	147834	143532	0	0
T5	211541	551634	0	0
T6	11744	9209	0	0
T7	119447	119213	0	0
T8	208128	207957	0	0
T9	28401	26132	0	0
T10	334921	333892	0	0

KmacDataODataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	197485304	197307635	0	0
T1	9327	9264	0	0
T2	111284	111230	0	0
T3	460412	457752	0	0
T4	147834	147735	0	0
T5	211541	211529	0	0
T6	11744	11430	0	0
T7	119447	119377	0	0
T8	208128	208053	0	0
T9	28401	27916	0	0
T10	334921	334789	0	0

KmacDataOValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197485304	197307635	0	0
T1	9327	9264	0	0
T2	111284	111230	0	0
T3	460412	457752	0	0
T4	147834	147735	0	0
T5	211541	211529	0	0
T6	11744	11430	0	0
T7	119447	119377	0	0
T8	208128	208053	0	0
T9	28401	27916	0	0
T10	334921	334789	0	0

PwrmgrDataChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197485304	0	0	324

PwrmgrDataOKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197485304	197307635	0	0
T1	9327	9264	0	0
T2	111284	111230	0	0
T3	460412	457752	0	0
T4	147834	147735	0	0
T5	211541	211529	0	0
T6	11744	11430	0	0
T7	119447	119377	0	0
T8	208128	208053	0	0
T9	28401	27916	0	0
T10	334921	334789	0	0

RegsTlOAReadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197485304	197307635	0	0
T1	9327	9264	0	0
T2	111284	111230	0	0
T3	460412	457752	0	0
T4	147834	147735	0	0
T5	211541	211529	0	0
T6	11744	11430	0	0
T7	119447	119377	0	0
T8	208128	208053	0	0
T9	28401	27916	0	0
T10	334921	334789	0	0

RegsTlODDataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197485304	7485386	0	0
T3	460412	100	0	0
T4	147834	64	0	0
T5	211541	298550	0	0
T6	11744	74	0	0
T7	119447	3	0	0
T8	208128	10	0	0
T9	28401	32	0	0
T10	334921	32	0	0
T15	18010	129	0	0
T33	8558	6	0	0

RegsTlODDataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	197485304	197307635	0	0
T1	9327	9264	0	0
T2	111284	111230	0	0
T3	460412	457752	0	0
T4	147834	147735	0	0
T5	211541	211529	0	0
T6	11744	11430	0	0
T7	119447	119377	0	0
T8	208128	208053	0	0
T9	28401	27916	0	0
T10	334921	334789	0	0

RegsTlODValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197485304	197307635	0	0
T1	9327	9264	0	0
T2	111284	111230	0	0
T3	460412	457752	0	0
T4	147834	147735	0	0
T5	211541	211529	0	0
T6	11744	11430	0	0
T7	119447	119377	0	0
T8	208128	208053	0	0
T9	28401	27916	0	0
T10	334921	334789	0	0

RomTlOAReadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197485304	197307635	0	0
T1	9327	9264	0	0
T2	111284	111230	0	0
T3	460412	457752	0	0
T4	147834	147735	0	0
T5	211541	211529	0	0
T6	11744	11430	0	0
T7	119447	119377	0	0
T8	208128	208053	0	0
T9	28401	27916	0	0
T10	334921	334789	0	0

RomTlODDataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197485304	16563616	0	0
T1	9327	207	0	0
T2	111284	51	0	0
T3	460412	4	0	0
T4	147834	131	0	0
T5	211541	374059	0	0
T6	11744	73	0	0
T7	119447	0	0	0
T8	208128	0	0	0
T9	28401	486	0	0
T10	334921	62	0	0
T15	0	74	0	0
T16	0	80	0	0

RomTlODDataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	197485304	197307635	0	0
T1	9327	9264	0	0
T2	111284	111230	0	0
T3	460412	457752	0	0
T4	147834	147735	0	0
T5	211541	211529	0	0
T6	11744	11430	0	0
T7	119447	119377	0	0
T8	208128	208053	0	0
T9	28401	27916	0	0
T10	334921	334789	0	0

RomTlODValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197485304	197307635	0	0
T1	9327	9264	0	0
T2	111284	111230	0	0
T3	460412	457752	0	0
T4	147834	147735	0	0
T5	211541	211529	0	0
T6	11744	11430	0	0
T7	119447	119377	0	0
T8	208128	208053	0	0
T9	28401	27916	0	0
T10	334921	334789	0	0

StabilityChkKmac_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197485304	127512767	0	0
T1	9327	8183	0	0
T2	111284	110083	0	0
T3	460412	429307	0	0
T4	147834	143531	0	0
T5	211541	551629	0	0
T6	11744	9205	0	0
T7	119447	119212	0	0
T8	208128	207956	0	0
T9	28401	26126	0	0
T10	334921	333890	0	0

StabilityChkkeymgr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197485304	69666688	0	0
T1	9327	1058	0	0
T2	111284	1105	0	0
T3	460412	26490	0	0
T4	147834	4138	0	0
T5	211541	156341	0	0
T6	11744	2193	0	0
T7	119447	60	0	0
T8	208128	63	0	0
T9	28401	1712	0	0
T10	334921	744	0	0

TlAccessChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197485304	127639765	0	0
T1	9327	8205	0	0
T2	111284	110124	0	0
T3	460412	431248	0	0
T4	147834	143596	0	0
T5	211541	551874	0	0
T6	11744	9236	0	0
T7	119447	119316	0	0
T8	208128	207989	0	0
T9	28401	26201	0	0
T10	334921	334043	0	0

gen_asserts_with_scrambling.FpvSecCmCheckerFsmAlert_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197485304	90	0	0
T24	309997	0	0	0
T27	989759	0	0	0
T30	217233	20	0	0
T31	0	20	0	0
T32	0	10	0	0
T35	0	20	0	0
T36	0	20	0	0
T37	17558	0	0	0
T38	42957	0	0	0
T39	135451	0	0	0
T40	134714	0	0	0
T41	582575	0	0	0
T42	74454	0	0	0
T43	20543	0	0	0

gen_asserts_with_scrambling.FpvSecCmCompareAddrCtrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197485304	0	0	0

gen_asserts_with_scrambling.FpvSecCmCompareFsmAlert_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197485304	533	0	0
T3	460412	5	0	0
T4	147834	0	0	0
T5	211541	0	0	0
T6	11744	0	0	0
T7	119447	0	0	0
T8	208128	0	0	0
T9	28401	0	0	0
T10	334921	0	0	0
T15	18010	0	0	0
T20	0	6	0	0
T25	0	5	0	0
T27	0	5	0	0
T28	0	6	0	0
T29	0	30	0	0
T30	0	20	0	0
T33	8558	0	0	0
T44	0	15	0	0
T45	0	5	0	0
T46	0	10	0	0

gen_fsm_scramble_enabled_asserts.BusLocalEscChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197485304	0	0	0