Unified Coverage Report :: Module :: rom_ctrl_regs_csr_assert_fpv

Module : rom_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rom_ctrl_csr_assert_0/rom_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rom_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rom_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.98	100.00	98.28	97.33		100.00	79.31	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rom_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	218126327	2342181	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218126327	2342181	0	0
T5	211541	52337	0	0
T6	11744	0	0	0
T7	119447	0	0	0
T8	208128	0	0	0
T9	28401	0	0	0
T10	334921	0	0	0
T11	0	292587	0	0
T12	0	67070	0	0
T15	18010	0	0	0
T16	142777	0	0	0
T33	8558	0	0	0
T34	147419	0	0	0
T47	0	135777	0	0
T48	0	51694	0	0
T49	0	65008	0	0
T50	0	28879	0	0
T51	0	513847	0	0
T52	0	66659	0	0
T53	0	72911	0	0