Line Coverage for Module :
rom_ctrl_compare
| Line No. | Total | Covered | Percent |
TOTAL | | 24 | 24 | 100.00 |
ALWAYS | 85 | 3 | 3 | 100.00 |
ALWAYS | 88 | 7 | 7 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 114 | 1 | 1 | 100.00 |
CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
CONT_ASSIGN | 125 | 1 | 1 | 100.00 |
CONT_ASSIGN | 148 | 1 | 1 | 100.00 |
CONT_ASSIGN | 149 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 152 | 1 | 1 | 100.00 |
ALWAYS | 154 | 4 | 4 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 177 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl_compare.sv' or '../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl_compare.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
85 |
3 |
3 |
88 |
1 |
1 |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
2 |
2 |
|
|
|
MISSING_ELSE |
95 |
2 |
2 |
|
|
|
MISSING_ELSE |
108 |
1 |
1 |
114 |
1 |
1 |
120 |
1 |
1 |
125 |
1 |
1 |
148 |
1 |
1 |
149 |
1 |
1 |
150 |
1 |
1 |
152 |
1 |
1 |
154 |
1 |
1 |
155 |
1 |
1 |
157 |
1 |
1 |
158 |
1 |
1 |
|
|
|
MISSING_ELSE |
163 |
1 |
1 |
177 |
1 |
1 |
Cond Coverage for Module :
rom_ctrl_compare
| Total | Covered | Percent |
Conditions | 43 | 41 | 95.35 |
Logical | 43 | 41 | 95.35 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 95
EXPRESSION (addr_q == LastAddr)
----------1---------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 108
EXPRESSION (start_i && (state_q != Waiting))
---1--- ----------2---------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T2,T7,T23 |
LINE 108
SUB-EXPRESSION (state_q != Waiting)
----------1---------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 114
EXPRESSION ((state_q == Waiting) && (addr_q != '0))
----------1--------- -------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T2,T19,T23 |
LINE 114
SUB-EXPRESSION (state_q == Waiting)
----------1---------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 114
SUB-EXPRESSION (addr_q != '0)
-------1------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 120
EXPRESSION ((state_q == Done) && (addr_q != LastAddr))
--------1-------- ----------2---------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T2,T7,T19 |
LINE 120
SUB-EXPRESSION (state_q == Done)
--------1--------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 120
SUB-EXPRESSION (addr_q != LastAddr)
----------1---------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 125
EXPRESSION ((state_q == Checking) && (addr_q != LastAddr))
----------1---------- ----------2---------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (state_q == Checking)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (addr_q != LastAddr)
----------1---------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 152
EXPRESSION (matches_q && (digest_word == exp_digest_word))
----1---- ----------------2---------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 152
SUB-EXPRESSION (digest_word == exp_digest_word)
----------------1---------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 157
EXPRESSION (state_q == Checking)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 163
EXPRESSION (state_q == Done)
--------1--------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 177
EXPRESSION (fsm_alert | start_alert | wait_addr_alert | done_addr_alert | addr_ctr_alert)
----1---- -----2----- -------3------- -------4------- -------5------
-1- | -2- | -3- | -4- | -5- | Status | Tests |
0 | 0 | 0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 0 | 0 | 1 | Not Covered | |
0 | 0 | 0 | 1 | 0 | Covered | T2,T7,T19 |
0 | 0 | 1 | 0 | 0 | Covered | T2,T19,T23 |
0 | 1 | 0 | 0 | 0 | Covered | T7,T23,T12 |
1 | 0 | 0 | 0 | 0 | Covered | T2,T7,T19 |
FSM Coverage for Module :
rom_ctrl_compare
Summary for FSM :: state_q
| Total | Covered | Percent | |
States |
3 |
3 |
100.00 |
(Not included in score) |
Transitions |
2 |
2 |
100.00 |
|
Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: state_q
| | | |
Checking |
92 |
Covered |
T1,T2,T3 |
Done |
95 |
Covered |
T1,T2,T3 |
Waiting |
91 |
Covered |
T1,T2,T3 |
| | | |
Checking->Done |
95 |
Covered |
T1,T2,T3 |
Waiting->Checking |
92 |
Covered |
T1,T2,T3 |
Branch Coverage for Module :
rom_ctrl_compare
| Line No. | Total | Covered | Percent |
Branches |
|
11 |
11 |
100.00 |
IF |
85 |
2 |
2 |
100.00 |
CASE |
90 |
6 |
6 |
100.00 |
IF |
154 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl_compare.sv' or '../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl_compare.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 85 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 90 case (state_q)
-2-: 92 if (start_i)
-3-: 95 if ((addr_q == LastAddr))
Branches:
-1- | -2- | -3- | Status | Tests |
Waiting |
1 |
- |
Covered |
T1,T2,T3 |
Waiting |
0 |
- |
Covered |
T1,T2,T3 |
Checking |
- |
1 |
Covered |
T1,T2,T3 |
Checking |
- |
0 |
Covered |
T1,T2,T3 |
Done |
- |
- |
Covered |
T1,T2,T3 |
default |
- |
- |
Covered |
T2,T7,T19 |
LineNo. Expression
-1-: 154 if ((!rst_ni))
-2-: 157 if ((state_q == Checking))
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
rom_ctrl_compare
Assertion Details
NumWordsPositive_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
318 |
318 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
u_state_regs_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
173091908 |
172913397 |
0 |
0 |
T1 |
8563 |
8478 |
0 |
0 |
T2 |
202105 |
201847 |
0 |
0 |
T3 |
19662 |
19445 |
0 |
0 |
T4 |
9149 |
9075 |
0 |
0 |
T5 |
214653 |
214596 |
0 |
0 |
T6 |
143437 |
143375 |
0 |
0 |
T7 |
276182 |
275856 |
0 |
0 |
T8 |
90266 |
90198 |
0 |
0 |
T9 |
107146 |
107012 |
0 |
0 |
T10 |
237811 |
237670 |
0 |
0 |