SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
87.50 | 87.50 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
rom_ctrl_tlul_cg | 87.50 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
87.50 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 8 | 1 | 7 | 87.50 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_regs_req_check | 3 | 0 | 3 | 100.00 | 100 | 1 | 1 | 0 | |
cp_rom_invalid_condition | 2 | 1 | 1 | 50.00 | 100 | 1 | 1 | 0 | |
cp_rom_req_check | 3 | 0 | 3 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 3 | 0 | 3 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
req_after_done | 1641098 | 1 | T1 | 154062 | T2 | 96 | T4 | 7600 | ||||
req_and_done | 13 | 1 | T46 | 1 | T96 | 3 | T63 | 1 | ||||
req_before_done | 11 | 1 | T44 | 1 | T99 | 1 | T68 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
check_invalid | 0 | 1 | 1 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
check_valid | 204052463 | 1 | T1 | 348974 | T2 | 337063 | T3 | 190339 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 3 | 0 | 3 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
req_after_done | 1735298 | 1 | T1 | 190822 | T2 | 157 | T4 | 1381 | ||||
req_and_done | 72 | 1 | T4 | 2 | T5 | 1 | T9 | 1 | ||||
req_before_done | 314 | 1 | T1 | 9 | T2 | 3 | T4 | 2 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |