Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3295386

1

T1

147258

T2

156

T4

117640

full_word

1416866

1

T1

65027

T2

19

T4

51436

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	4711942	1			T1	212285		T2	175		T4	169076
auto[TlIntgErrCmd]	95	1			T47	5		T48	5		T49	5
auto[TlIntgErrData]	100	1			T47	8		T48	7		T49	2
auto[TlIntgErrBoth]	115	1			T47	7		T48	8		T49	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

574442

1

T1

25577

T2

175

T4

19698

auto[1]

4137810

1

T1

186708

T4

149378

T11

145530

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	247109	1			T1	10524		T2	156		T4	8009
auto[TlIntgErrNone]	partial	auto[1]	3047994	1			T1	136734		T4	109631		T11	106769
auto[TlIntgErrNone]	full_word	auto[0]	327205	1			T1	15053		T2	19		T4	11689
auto[TlIntgErrNone]	full_word	auto[1]	1089634	1			T1	49974		T4	39747		T11	38761
auto[TlIntgErrCmd]	partial	auto[0]	33	1			T47	2		T48	2		T49	1
auto[TlIntgErrCmd]	partial	auto[1]	55	1			T47	3		T48	3		T49	4
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T107	1		T105	1		T103	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T101	1		T102	1		T108	1
auto[TlIntgErrData]	partial	auto[0]	42	1			T47	4		T48	1		T100	2
auto[TlIntgErrData]	partial	auto[1]	45	1			T47	4		T48	5		T49	2
auto[TlIntgErrData]	full_word	auto[0]	7	1			T107	1		T104	1		T102	2
auto[TlIntgErrData]	full_word	auto[1]	6	1			T48	1		T105	1		T109	1
auto[TlIntgErrBoth]	partial	auto[0]	41	1			T47	3		T48	5		T49	1
auto[TlIntgErrBoth]	partial	auto[1]	67	1			T47	4		T48	3		T49	1
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T49	1		T105	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T110	1		T111	1		T112	1