Module Definition
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Module : rom_ctrl_scrambled_rom
SCORELINECONDTOGGLEFSMBRANCHASSERT
87.50 75.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl_scrambled_rom.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.gen_rom_scramble_enabled.u_rom 87.50 75.00 100.00



Module Instance : tb.dut.gen_rom_scramble_enabled.u_rom

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
87.50 75.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.06 88.24 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.98 100.00 98.28 97.33 100.00 79.31 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prince 100.00 100.00
u_rom 94.44 83.33 100.00 100.00
u_seed_anchor 0.00 0.00
u_sp_addr 100.00 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : rom_ctrl_scrambled_rom
Line No.TotalCoveredPercent
TOTAL4375.00
CONT_ASSIGN81100.00
CONT_ASSIGN8200
CONT_ASSIGN12811100.00
CONT_ASSIGN14911100.00
CONT_ASSIGN15311100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl_scrambled_rom.sv' or '../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl_scrambled_rom.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
81 0 1
82 unreachable
128 1 1
149 1 1
153 1 1


Assert Coverage for Module : rom_ctrl_scrambled_rom
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DepthPow2Check_A 321 321 0 0
MaxWidthCheck_A 321 321 0 0


DepthPow2Check_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 321 321 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

MaxWidthCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 321 321 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%