Line Coverage for Module :
prim_mubi4_sender
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
82 |
1 |
1 |
85 |
1 |
1 |
Assert Coverage for Module :
prim_mubi4_sender
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
182581523 |
182408356 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
182581523 |
182408356 |
0 |
0 |
T1 |
348974 |
348953 |
0 |
0 |
T2 |
337062 |
336763 |
0 |
0 |
T3 |
190339 |
188165 |
0 |
0 |
T4 |
196485 |
196470 |
0 |
0 |
T5 |
124268 |
124188 |
0 |
0 |
T6 |
240984 |
240838 |
0 |
0 |
T7 |
63345 |
62778 |
0 |
0 |
T8 |
41273 |
41098 |
0 |
0 |
T9 |
33634 |
33547 |
0 |
0 |
T10 |
377428 |
377271 |
0 |
0 |