Unified Coverage Report :: Module :: rom_ctrl

Module : rom_ctrl

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.98	100.00	98.28	97.33		100.00	79.31

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	94.98	100.00	98.28	97.33		100.00	79.31

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.98	100.00	98.28	97.33		100.00	79.31

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.33	97.04	92.65	97.88	100.00	98.37	98.04

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_alert_tx[0].u_alert_sender	100.00			100.00
gen_fsm_scramble_enabled.u_checker_fsm	95.92	100.00	96.30	90.00	100.00	98.31	90.91
gen_rom_scramble_enabled.u_rom	97.06	88.24		100.00		100.00	100.00
regs_tlul_assert_device	100.00	100.00				100.00	100.00
rom_ctrl_regs_csr_assert	100.00						100.00
rom_tlul_assert_device	99.30	100.00				100.00	97.90
u_mux	95.24	100.00	85.71			100.00
u_reg_regs	99.72	99.41	99.21	100.00		100.00	100.00
u_rom_top	100.00	100.00				100.00	100.00
u_tl_adapter_rom	93.77	91.56	83.06	99.07		95.18	100.00
u_tl_rom_h2d_buf	100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rom_ctrl

	Line No.	Total	Covered	Percent
TOTAL		65	65	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	123	1	1	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	221	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	322	1	1	100.00
CONT_ASSIGN	423	1	1	100.00
CONT_ASSIGN	423	1	1	100.00
CONT_ASSIGN	423	1	1	100.00
CONT_ASSIGN	423	1	1	100.00
CONT_ASSIGN	423	1	1	100.00
CONT_ASSIGN	423	1	1	100.00
CONT_ASSIGN	423	1	1	100.00
CONT_ASSIGN	423	1	1	100.00
CONT_ASSIGN	424	1	1	100.00
CONT_ASSIGN	424	1	1	100.00
CONT_ASSIGN	424	1	1	100.00
CONT_ASSIGN	424	1	1	100.00
CONT_ASSIGN	424	1	1	100.00
CONT_ASSIGN	424	1	1	100.00
CONT_ASSIGN	424	1	1	100.00
CONT_ASSIGN	424	1	1	100.00
CONT_ASSIGN	426	1	1	100.00
CONT_ASSIGN	426	1	1	100.00
CONT_ASSIGN	426	1	1	100.00
CONT_ASSIGN	426	1	1	100.00
CONT_ASSIGN	426	1	1	100.00
CONT_ASSIGN	426	1	1	100.00
CONT_ASSIGN	426	1	1	100.00
CONT_ASSIGN	426	1	1	100.00
CONT_ASSIGN	427	1	1	100.00
CONT_ASSIGN	427	1	1	100.00
CONT_ASSIGN	427	1	1	100.00
CONT_ASSIGN	427	1	1	100.00
CONT_ASSIGN	427	1	1	100.00
CONT_ASSIGN	427	1	1	100.00
CONT_ASSIGN	427	1	1	100.00
CONT_ASSIGN	427	1	1	100.00
CONT_ASSIGN	429	1	1	100.00
CONT_ASSIGN	429	1	1	100.00
CONT_ASSIGN	429	1	1	100.00
CONT_ASSIGN	429	1	1	100.00
CONT_ASSIGN	429	1	1	100.00
CONT_ASSIGN	429	1	1	100.00
CONT_ASSIGN	429	1	1	100.00
CONT_ASSIGN	429	1	1	100.00
CONT_ASSIGN	430	1	1	100.00
CONT_ASSIGN	430	1	1	100.00
CONT_ASSIGN	430	1	1	100.00
CONT_ASSIGN	430	1	1	100.00
CONT_ASSIGN	430	1	1	100.00
CONT_ASSIGN	430	1	1	100.00
CONT_ASSIGN	430	1	1	100.00
CONT_ASSIGN	430	1	1	100.00
CONT_ASSIGN	434	1	1	100.00
CONT_ASSIGN	436	1	1	100.00
CONT_ASSIGN	439	1	1	100.00
CONT_ASSIGN	440	1	1	100.00
CONT_ASSIGN	441	1	1	100.00
CONT_ASSIGN	442	1	1	100.00
CONT_ASSIGN	447	1	1	100.00
CONT_ASSIGN	451	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv' or '../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
118	1	1
123	1	1
124	1	1
125	1	1
126	1	1
129	1	1
221	1	1
267	1	1
322	1	1
423	8	8
424	8	8
426	8	8
427	8	8
429	8	8
430	8	8
434	1	1
436	1	1
439	1	1
440	1	1
441	1	1
442	1	1
447	1	1
451	1	1

---

Cond Coverage for Module : rom_ctrl

	Total	Covered	Percent
Conditions	58	57	98.28
Logical	58	57	98.28
Non-Logical	0	0
Event	0	0

 LINE       221
 EXPRESSION (tl_rom_h2d_upstream.a_valid ? tl_rom_h2d_upstream.a_address[2+:RomIndexWidth] : '0)
             -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       267
 EXPRESSION (bus_rom_rvalid_raw & ((!internal_alert)))
             ---------1--------   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T10,T27,T19
1	1	Covered	T1,T2,T4

 LINE       427
 EXPRESSION (exp_digest_de && (0[2:0] == exp_digest_idx))
             ------1------    -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       427
 SUB-EXPRESSION (0[2:0] == exp_digest_idx)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       427
 EXPRESSION (exp_digest_de && (1[2:0] == exp_digest_idx))
             ------1------    -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       427
 SUB-EXPRESSION (1[2:0] == exp_digest_idx)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       427
 EXPRESSION (exp_digest_de && (2[2:0] == exp_digest_idx))
             ------1------    -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       427
 SUB-EXPRESSION (2[2:0] == exp_digest_idx)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       427
 EXPRESSION (exp_digest_de && (3[2:0] == exp_digest_idx))
             ------1------    -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       427
 SUB-EXPRESSION (3[2:0] == exp_digest_idx)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       427
 EXPRESSION (exp_digest_de && (4[2:0] == exp_digest_idx))
             ------1------    -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       427
 SUB-EXPRESSION (4[2:0] == exp_digest_idx)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       427
 EXPRESSION (exp_digest_de && (5[2:0] == exp_digest_idx))
             ------1------    -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       427
 SUB-EXPRESSION (5[2:0] == exp_digest_idx)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       427
 EXPRESSION (exp_digest_de && (6[2:0] == exp_digest_idx))
             ------1------    -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       427
 SUB-EXPRESSION (6[2:0] == exp_digest_idx)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       427
 EXPRESSION (exp_digest_de && (7[2:0] == exp_digest_idx))
             ------1------    -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       427
 SUB-EXPRESSION (7[2:0] == exp_digest_idx)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       434
 EXPRESSION (rom_reg_integrity_error | rom_integrity_error | reg_integrity_error)
             -----------1-----------   ---------2---------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T23,T30,T31
0	1	0	Not Covered
1	0	0	Unreachable

 LINE       436
 EXPRESSION (checker_alert | mux_alert)
             ------1------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T27,T19
1	0	Covered	T7,T9,T10

 LINE       447
 EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
             ---------1---------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T3,T32,T33
1	0	Covered	T1,T3,T4
1	1	Covered	T3,T32,T33

 LINE       451
 EXPRESSION (bus_integrity_error | checker_alert | mux_alert)
             ---------1---------   ------2------   ----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T10,T27,T19
0	1	0	Covered	T7,T9,T10
1	0	0	Covered	T23,T30,T31

---

Toggle Coverage for Module : rom_ctrl

	Total	Covered	Percent
Totals	61	56	91.80
Total Bits	2882	2805	97.33
Total Bits 0->1	1441	1402	97.29
Total Bits 1->0	1441	1403	97.36

Ports	61	56	91.80
Port Bits	2882	2805	97.33
Port Bits 0->1	1441	1402	97.29
Port Bits 1->0	1441	1403	97.36

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	INPUT
rom_cfg_i.cfg[3:0]	No	No		No		INPUT
rom_cfg_i.cfg_en	No	No		No		INPUT
rom_tl_i.d_ready	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
rom_tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
rom_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
rom_tl_i.a_user.instr_type[3:0]	Yes	Yes	T6,T11,T13	Yes	T6,T14,T13	INPUT
rom_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
rom_tl_i.a_data[31:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
rom_tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
rom_tl_i.a_address[31:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
rom_tl_i.a_source[7:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
rom_tl_i.a_size[1:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
rom_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
rom_tl_i.a_opcode[2:0]	Yes	Yes	T6,T11,T14	Yes	T6,T13,T34	INPUT
rom_tl_i.a_valid	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
rom_tl_o.a_ready	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	OUTPUT
rom_tl_o.d_error	Yes	Yes	T13,T15,T16	Yes	T13,T15,T16	OUTPUT
rom_tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
rom_tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T4	Yes	T1,T2,T4	OUTPUT
rom_tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
rom_tl_o.d_data[31:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
rom_tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
rom_tl_o.d_source[7:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
rom_tl_o.d_size[1:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
rom_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
rom_tl_o.d_opcode[0]	Yes	Yes	*T13,*T15,*T16	Yes	T13,T15,T16	OUTPUT
rom_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
rom_tl_o.d_valid	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
regs_tl_i.d_ready	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
regs_tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
regs_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
regs_tl_i.a_user.instr_type[3:0]	Yes	Yes	T3,T19,T13	Yes	T3,T19,T13	INPUT
regs_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_data[31:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
regs_tl_i.a_mask[3:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
regs_tl_i.a_address[31:0]	Yes	Yes	T1,T3,T5	Yes	T1,T3,T5	INPUT
regs_tl_i.a_source[7:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
regs_tl_i.a_size[1:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
regs_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_opcode[2:0]	Yes	Yes	T3,T19,T13	Yes	T3,T19,T13	INPUT
regs_tl_i.a_valid	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
regs_tl_o.a_ready	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
regs_tl_o.d_error	Yes	Yes	T13,T15,T16	Yes	T13,T15,T16	OUTPUT
regs_tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
regs_tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T4,*T5	Yes	T1,T3,T4	OUTPUT
regs_tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_data[31:0]	Yes	Yes	T1,T4,T5	Yes	T1,T3,T4	OUTPUT
regs_tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_source[7:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
regs_tl_o.d_size[1:0]	Yes	Yes	T1,T4,T5	Yes	T1,T3,T4	OUTPUT
regs_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_opcode[0]	Yes	Yes	*T1,*T4,*T5	Yes	T1,T4,T5	OUTPUT
regs_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_valid	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T3,T7,T9	Yes	T3,T7,T9	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T3,T7,T9	Yes	T3,T7,T9	OUTPUT
pwrmgr_data_o.good[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
pwrmgr_data_o.done[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T4,T5	OUTPUT
keymgr_data_o.valid	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	OUTPUT
keymgr_data_o.data[255:0]	Yes	Yes	T1,T8,T10	Yes	T1,T4,T5	OUTPUT
kmac_data_i.error	No	Yes	T7,T9,T14	No		INPUT
kmac_data_i.digest_share1[383:0]	Yes	Yes	T5,T8,T10	Yes	T5,T10,T27	INPUT
kmac_data_i.digest_share0[383:0]	Yes	Yes	T4,T5,T7	Yes	T10,T27,T19	INPUT
kmac_data_i.done	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
kmac_data_i.ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
kmac_data_o.last	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
kmac_data_o.strb[7:0]	No	No		No		OUTPUT
kmac_data_o.data[38:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
kmac_data_o.data[63:39]	No	No		No		OUTPUT
kmac_data_o.valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Module : rom_ctrl

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
TERNARY	221	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv' or '../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	221	(tl_rom_h2d_upstream.a_valid) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Module : rom_ctrl

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	29	29	100.00	23	79.31
Cover properties	0	0		0
Cover sequences	0	0		0
Total	29	29	100.00	23	79.31

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxOKnown_A	180888642	180727732	0	0
BusRomIndicesMatch_A	180877039	180722647	0	0
FpvSecCmFifoRptrCheck_A	180888642	0	0	0
FpvSecCmFifoWptrCheck_A	180888642	0	0	0
FpvSecCmRegWeOnehotCheck_A	180888642	60	0	0
KeymgrDataODataKnown_A	180888642	54537675	0	0
KeymgrDataODataKnown_AKnownEnable	180888642	180727732	0	0
KeymgrDataOValidKnown_A	180888642	180727732	0	0
KeymgrValidChk_A	180888642	0	0	319
KmacDataODataKnown_A	180888642	126078631	0	0
KmacDataODataKnown_AKnownEnable	180888642	180727732	0	0
KmacDataOValidKnown_A	180888642	180727732	0	0
PwrmgrDataChk_A	180888642	0	0	319
PwrmgrDataOKnown_A	180888642	180727732	0	0
RegsTlOAReadyKnown_A	180888642	180727732	0	0
RegsTlODDataKnown_A	180888642	7175218	0	0
RegsTlODDataKnown_AKnownEnable	180888642	180727732	0	0
RegsTlODValidKnown_A	180888642	180727732	0	0
RomTlOAReadyKnown_A	180888642	180727732	0	0
RomTlODDataKnown_A	180888642	11803173	0	0
RomTlODDataKnown_AKnownEnable	180888642	180727732	0	0
RomTlODValidKnown_A	180888642	180727732	0	0
StabilityChkKmac_A	180888642	126076393	0	0
StabilityChkkeymgr_A	180888642	54536539	0	0
TlAccessChk_A	180888642	126190057	0	0
gen_asserts_with_scrambling.FpvSecCmCheckerFsmAlert_A	180888642	60	0	0
gen_asserts_with_scrambling.FpvSecCmCompareAddrCtrCheck_A	180888642	0	0	0
gen_asserts_with_scrambling.FpvSecCmCompareFsmAlert_A	180888642	427	0	0
gen_fsm_scramble_enabled_asserts.BusLocalEscChk_A	180888642	0	0	0

AlertTxOKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	180888642	180727732	0	0
T1	312420	312292	0	0
T2	42017	41967	0	0
T3	74470	74387	0	0
T4	382263	382152	0	0
T5	383385	383034	0	0
T6	193229	193146	0	0
T7	204798	204664	0	0
T8	447089	446829	0	0
T9	16632	16471	0	0
T10	550127	548317	0	0

BusRomIndicesMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	180877039	180722647	0	0
T1	312420	312292	0	0
T2	42017	41967	0	0
T3	74470	74387	0	0
T4	382263	382152	0	0
T5	383385	383034	0	0
T6	193229	193146	0	0
T7	204798	204664	0	0
T8	447089	446829	0	0
T9	16632	16471	0	0
T10	550014	548296	0	0

FpvSecCmFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	180888642	0	0	0

FpvSecCmFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	180888642	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	180888642	60	0	0
T23	142182	10	0	0
T24	639189	0	0	0
T30	0	10	0	0
T31	0	20	0	0
T35	0	10	0	0
T36	0	10	0	0
T37	239536	0	0	0
T38	167358	0	0	0
T39	581033	0	0	0
T40	141827	0	0	0
T41	147226	0	0	0
T42	37715	0	0	0
T43	16567	0	0	0
T44	172786	0	0	0

KeymgrDataODataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	180888642	54537675	0	0
T1	312420	1730	0	0
T2	42017	1182	0	0
T3	74470	289	0	0
T4	382263	1761	0	0
T5	383385	3040	0	0
T6	193229	1316	0	0
T7	204798	67	0	0
T8	447089	3976	0	0
T9	16632	47	0	0
T10	550127	11703	0	0

KeymgrDataODataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	180888642	180727732	0	0
T1	312420	312292	0	0
T2	42017	41967	0	0
T3	74470	74387	0	0
T4	382263	382152	0	0
T5	383385	383034	0	0
T6	193229	193146	0	0
T7	204798	204664	0	0
T8	447089	446829	0	0
T9	16632	16471	0	0
T10	550127	548317	0	0

KeymgrDataOValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	180888642	180727732	0	0
T1	312420	312292	0	0
T2	42017	41967	0	0
T3	74470	74387	0	0
T4	382263	382152	0	0
T5	383385	383034	0	0
T6	193229	193146	0	0
T7	204798	204664	0	0
T8	447089	446829	0	0
T9	16632	16471	0	0
T10	550127	548317	0	0

KeymgrValidChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	180888642	0	0	319

KmacDataODataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	180888642	126078631	0	0
T1	312420	310379	0	0
T2	42017	40751	0	0
T3	74470	73991	0	0
T4	382263	380261	0	0
T5	383385	379771	0	0
T6	193229	191791	0	0
T7	204798	204438	0	0
T8	447089	442692	0	0
T9	16632	16368	0	0
T10	550127	535418	0	0

KmacDataODataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	180888642	180727732	0	0
T1	312420	312292	0	0
T2	42017	41967	0	0
T3	74470	74387	0	0
T4	382263	382152	0	0
T5	383385	383034	0	0
T6	193229	193146	0	0
T7	204798	204664	0	0
T8	447089	446829	0	0
T9	16632	16471	0	0
T10	550127	548317	0	0

KmacDataOValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	180888642	180727732	0	0
T1	312420	312292	0	0
T2	42017	41967	0	0
T3	74470	74387	0	0
T4	382263	382152	0	0
T5	383385	383034	0	0
T6	193229	193146	0	0
T7	204798	204664	0	0
T8	447089	446829	0	0
T9	16632	16471	0	0
T10	550127	548317	0	0

PwrmgrDataChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	180888642	0	0	319

PwrmgrDataOKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	180888642	180727732	0	0
T1	312420	312292	0	0
T2	42017	41967	0	0
T3	74470	74387	0	0
T4	382263	382152	0	0
T5	383385	383034	0	0
T6	193229	193146	0	0
T7	204798	204664	0	0
T8	447089	446829	0	0
T9	16632	16471	0	0
T10	550127	548317	0	0

RegsTlOAReadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	180888642	180727732	0	0
T1	312420	312292	0	0
T2	42017	41967	0	0
T3	74470	74387	0	0
T4	382263	382152	0	0
T5	383385	383034	0	0
T6	193229	193146	0	0
T7	204798	204664	0	0
T8	447089	446829	0	0
T9	16632	16471	0	0
T10	550127	548317	0	0

RegsTlODDataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	180888642	7175218	0	0
T1	312420	32	0	0
T2	42017	0	0	0
T3	74470	11	0	0
T4	382263	32	0	0
T5	383385	64	0	0
T6	193229	0	0	0
T7	204798	8	0	0
T8	447089	285	0	0
T9	16632	7	0	0
T10	550127	19	0	0
T27	0	20	0	0
T32	0	6	0	0

RegsTlODDataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	180888642	180727732	0	0
T1	312420	312292	0	0
T2	42017	41967	0	0
T3	74470	74387	0	0
T4	382263	382152	0	0
T5	383385	383034	0	0
T6	193229	193146	0	0
T7	204798	204664	0	0
T8	447089	446829	0	0
T9	16632	16471	0	0
T10	550127	548317	0	0

RegsTlODValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	180888642	180727732	0	0
T1	312420	312292	0	0
T2	42017	41967	0	0
T3	74470	74387	0	0
T4	382263	382152	0	0
T5	383385	383034	0	0
T6	193229	193146	0	0
T7	204798	204664	0	0
T8	447089	446829	0	0
T9	16632	16471	0	0
T10	550127	548317	0	0

RomTlOAReadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	180888642	180727732	0	0
T1	312420	312292	0	0
T2	42017	41967	0	0
T3	74470	74387	0	0
T4	382263	382152	0	0
T5	383385	383034	0	0
T6	193229	193146	0	0
T7	204798	204664	0	0
T8	447089	446829	0	0
T9	16632	16471	0	0
T10	550127	548317	0	0

RomTlODDataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	180888642	11803173	0	0
T1	312420	275	0	0
T2	42017	137	0	0
T3	74470	0	0	0
T4	382263	475	0	0
T5	383385	135	0	0
T6	193229	289	0	0
T7	204798	0	0	0
T8	447089	119	0	0
T9	16632	0	0	0
T10	550127	3	0	0
T11	0	93	0	0
T19	0	22	0	0
T20	0	20	0	0

RomTlODDataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	180888642	180727732	0	0
T1	312420	312292	0	0
T2	42017	41967	0	0
T3	74470	74387	0	0
T4	382263	382152	0	0
T5	383385	383034	0	0
T6	193229	193146	0	0
T7	204798	204664	0	0
T8	447089	446829	0	0
T9	16632	16471	0	0
T10	550127	548317	0	0

RomTlODValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	180888642	180727732	0	0
T1	312420	312292	0	0
T2	42017	41967	0	0
T3	74470	74387	0	0
T4	382263	382152	0	0
T5	383385	383034	0	0
T6	193229	193146	0	0
T7	204798	204664	0	0
T8	447089	446829	0	0
T9	16632	16471	0	0
T10	550127	548317	0	0

StabilityChkKmac_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	180888642	126076393	0	0
T1	312420	310377	0	0
T2	42017	40750	0	0
T3	74470	73990	0	0
T4	382263	380259	0	0
T5	383385	379766	0	0
T6	193229	191790	0	0
T7	204798	204436	0	0
T8	447089	442688	0	0
T9	16632	16366	0	0
T10	550127	535394	0	0

StabilityChkkeymgr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	180888642	54536539	0	0
T1	312420	1728	0	0
T2	42017	1181	0	0
T3	74470	288	0	0
T4	382263	1759	0	0
T5	383385	3037	0	0
T6	193229	1315	0	0
T7	204798	66	0	0
T8	447089	3973	0	0
T9	16632	46	0	0
T10	550127	11693	0	0

TlAccessChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	180888642	126190057	0	0
T1	312420	310562	0	0
T2	42017	40785	0	0
T3	74470	74098	0	0
T4	382263	380391	0	0
T5	383385	379994	0	0
T6	193229	191830	0	0
T7	204798	204597	0	0
T8	447089	442853	0	0
T9	16632	16424	0	0
T10	550127	536614	0	0

gen_asserts_with_scrambling.FpvSecCmCheckerFsmAlert_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	180888642	60	0	0
T23	142182	10	0	0
T24	639189	0	0	0
T30	0	10	0	0
T31	0	20	0	0
T35	0	10	0	0
T36	0	10	0	0
T37	239536	0	0	0
T38	167358	0	0	0
T39	581033	0	0	0
T40	141827	0	0	0
T41	147226	0	0	0
T42	37715	0	0	0
T43	16567	0	0	0
T44	172786	0	0	0

gen_asserts_with_scrambling.FpvSecCmCompareAddrCtrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	180888642	0	0	0

gen_asserts_with_scrambling.FpvSecCmCompareFsmAlert_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	180888642	427	0	0
T10	550127	10	0	0
T11	166313	0	0	0
T14	278439	0	0	0
T19	182360	5	0	0
T20	361675	10	0	0
T26	198523	15	0	0
T27	543922	10	0	0
T28	130658	0	0	0
T29	0	5	0	0
T32	73999	0	0	0
T45	0	5	0	0
T46	0	6	0	0
T47	0	10	0	0
T48	0	10	0	0
T49	9433	0	0	0

gen_fsm_scramble_enabled_asserts.BusLocalEscChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	180888642	0	0	0