Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : rom_ctrl_regs_reg_top
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl_regs_reg_top.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_reg_regs 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg_regs

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.72 99.41 99.21 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.98 100.00 98.28 97.33 100.00 79.31 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_alert_test 100.00 100.00
u_chk 100.00 100.00 100.00 100.00
u_digest_0 100.00 100.00 100.00 100.00
u_digest_1 100.00 100.00 100.00 100.00
u_digest_2 100.00 100.00 100.00 100.00
u_digest_3 100.00 100.00 100.00 100.00
u_digest_4 100.00 100.00 100.00 100.00
u_digest_5 100.00 100.00 100.00 100.00
u_digest_6 100.00 100.00 100.00 100.00
u_digest_7 100.00 100.00 100.00 100.00
u_exp_digest_0 100.00 100.00 100.00 100.00
u_exp_digest_1 100.00 100.00 100.00 100.00
u_exp_digest_2 100.00 100.00 100.00 100.00
u_exp_digest_3 100.00 100.00 100.00 100.00
u_exp_digest_4 100.00 100.00 100.00 100.00
u_exp_digest_5 100.00 100.00 100.00 100.00
u_exp_digest_6 100.00 100.00 100.00 100.00
u_exp_digest_7 100.00 100.00 100.00 100.00
u_fatal_alert_cause_checker_error 100.00 100.00 100.00 100.00
u_fatal_alert_cause_integrity_error 100.00 100.00 100.00 100.00
u_prim_reg_we_check 100.00 100.00 100.00
u_reg_if 98.67 97.14 97.53 100.00 100.00
u_rsp_intg_gen 100.00 100.00 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : rom_ctrl_regs_reg_top
Line No.TotalCoveredPercent
TOTAL7676100.00
ALWAYS6844100.00
CONT_ASSIGN7711100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN9011100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN11911100.00
CONT_ASSIGN14911100.00
CONT_ASSIGN16311100.00
ALWAYS6891919100.00
CONT_ASSIGN71011100.00
ALWAYS71411100.00
CONT_ASSIGN73611100.00
CONT_ASSIGN73811100.00
ALWAYS7421919100.00
ALWAYS7652121100.00
CONT_ASSIGN85100
CONT_ASSIGN85911100.00
CONT_ASSIGN86011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl_regs_reg_top.sv' or '../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl_regs_reg_top.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
68 1 1
69 1 1
70 1 1
71 1 1
MISSING_ELSE
77 1 1
89 1 1
90 1 1
118 1 1
119 1 1
149 1 1
163 1 1
689 1 1
690 1 1
691 1 1
692 1 1
693 1 1
694 1 1
695 1 1
696 1 1
697 1 1
698 1 1
699 1 1
700 1 1
701 1 1
702 1 1
703 1 1
704 1 1
705 1 1
706 1 1
707 1 1
710 1 1
714 1 1
736 1 1
738 1 1
742 1 1
743 1 1
744 1 1
745 1 1
746 1 1
747 1 1
748 1 1
749 1 1
750 1 1
751 1 1
752 1 1
753 1 1
754 1 1
755 1 1
756 1 1
757 1 1
758 1 1
759 1 1
760 1 1
765 1 1
766 1 1
768 1 1
772 1 1
773 1 1
777 1 1
781 1 1
785 1 1
789 1 1
793 1 1
797 1 1
801 1 1
805 1 1
809 1 1
813 1 1
817 1 1
821 1 1
825 1 1
829 1 1
833 1 1
837 1 1
851 unreachable
859 1 1
860 1 1


Cond Coverage for Module : rom_ctrl_regs_reg_top
TotalCoveredPercent
Conditions135135100.00
Logical135135100.00
Non-Logical00
Event00

 LINE       58
 EXPRESSION (reg_we && ((!addrmiss)))
             ---1--    ------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT13,T15,T16
11CoveredT3,T32,T13

 LINE       70
 EXPRESSION (intg_err || reg_we_err)
             ----1---    -----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT23,T30,T31
10CoveredT61,T62,T63

 LINE       77
 EXPRESSION (err_q | intg_err | reg_we_err)
             --1--   ----2---   -----3----
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT23,T30,T31
010CoveredT61,T62,T63
100CoveredT23,T30,T31

 LINE       119
 EXPRESSION (addrmiss | wr_err | intg_err)
             ----1---   ---2--   ----3---
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT61,T62,T63
010CoveredT13,T15,T16
100CoveredT13,T15,T16

 LINE       690
 EXPRESSION (reg_addr == rom_ctrl_reg_pkg::ROM_CTRL_ALERT_TEST_OFFSET)
            -----------------------------1----------------------------
-1-StatusTests
0CoveredT1,T3,T4
1CoveredT3,T32,T19

 LINE       691
 EXPRESSION (reg_addr == rom_ctrl_reg_pkg::ROM_CTRL_FATAL_ALERT_CAUSE_OFFSET)
            --------------------------------1--------------------------------
-1-StatusTests
0CoveredT1,T3,T4
1CoveredT7,T9,T10

 LINE       692
 EXPRESSION (reg_addr == rom_ctrl_reg_pkg::ROM_CTRL_DIGEST_0_OFFSET)
            ----------------------------1---------------------------
-1-StatusTests
0CoveredT1,T3,T4
1CoveredT1,T4,T5

 LINE       693
 EXPRESSION (reg_addr == rom_ctrl_reg_pkg::ROM_CTRL_DIGEST_1_OFFSET)
            ----------------------------1---------------------------
-1-StatusTests
0CoveredT1,T3,T4
1CoveredT1,T4,T5

 LINE       694
 EXPRESSION (reg_addr == rom_ctrl_reg_pkg::ROM_CTRL_DIGEST_2_OFFSET)
            ----------------------------1---------------------------
-1-StatusTests
0CoveredT1,T3,T4
1CoveredT1,T4,T5

 LINE       695
 EXPRESSION (reg_addr == rom_ctrl_reg_pkg::ROM_CTRL_DIGEST_3_OFFSET)
            ----------------------------1---------------------------
-1-StatusTests
0CoveredT1,T3,T4
1CoveredT1,T4,T5

 LINE       696
 EXPRESSION (reg_addr == rom_ctrl_reg_pkg::ROM_CTRL_DIGEST_4_OFFSET)
            ----------------------------1---------------------------
-1-StatusTests
0CoveredT1,T3,T4
1CoveredT1,T4,T5

 LINE       697
 EXPRESSION (reg_addr == rom_ctrl_reg_pkg::ROM_CTRL_DIGEST_5_OFFSET)
            ----------------------------1---------------------------
-1-StatusTests
0CoveredT1,T3,T4
1CoveredT1,T3,T4

 LINE       698
 EXPRESSION (reg_addr == rom_ctrl_reg_pkg::ROM_CTRL_DIGEST_6_OFFSET)
            ----------------------------1---------------------------
-1-StatusTests
0CoveredT1,T3,T4
1CoveredT1,T4,T5

 LINE       699
 EXPRESSION (reg_addr == rom_ctrl_reg_pkg::ROM_CTRL_DIGEST_7_OFFSET)
            ----------------------------1---------------------------
-1-StatusTests
0CoveredT1,T3,T4
1CoveredT1,T3,T4

 LINE       700
 EXPRESSION (reg_addr == rom_ctrl_reg_pkg::ROM_CTRL_EXP_DIGEST_0_OFFSET)
            ------------------------------1-----------------------------
-1-StatusTests
0CoveredT1,T3,T4
1CoveredT1,T4,T5

 LINE       701
 EXPRESSION (reg_addr == rom_ctrl_reg_pkg::ROM_CTRL_EXP_DIGEST_1_OFFSET)
            ------------------------------1-----------------------------
-1-StatusTests
0CoveredT1,T3,T4
1CoveredT1,T4,T5

 LINE       702
 EXPRESSION (reg_addr == rom_ctrl_reg_pkg::ROM_CTRL_EXP_DIGEST_2_OFFSET)
            ------------------------------1-----------------------------
-1-StatusTests
0CoveredT1,T3,T4
1CoveredT1,T4,T5

 LINE       703
 EXPRESSION (reg_addr == rom_ctrl_reg_pkg::ROM_CTRL_EXP_DIGEST_3_OFFSET)
            ------------------------------1-----------------------------
-1-StatusTests
0CoveredT1,T3,T4
1CoveredT1,T3,T4

 LINE       704
 EXPRESSION (reg_addr == rom_ctrl_reg_pkg::ROM_CTRL_EXP_DIGEST_4_OFFSET)
            ------------------------------1-----------------------------
-1-StatusTests
0CoveredT1,T3,T4
1CoveredT1,T4,T5

 LINE       705
 EXPRESSION (reg_addr == rom_ctrl_reg_pkg::ROM_CTRL_EXP_DIGEST_5_OFFSET)
            ------------------------------1-----------------------------
-1-StatusTests
0CoveredT1,T3,T4
1CoveredT1,T4,T5

 LINE       706
 EXPRESSION (reg_addr == rom_ctrl_reg_pkg::ROM_CTRL_EXP_DIGEST_6_OFFSET)
            ------------------------------1-----------------------------
-1-StatusTests
0CoveredT1,T3,T4
1CoveredT1,T4,T5

 LINE       707
 EXPRESSION (reg_addr == rom_ctrl_reg_pkg::ROM_CTRL_EXP_DIGEST_7_OFFSET)
            ------------------------------1-----------------------------
-1-StatusTests
0CoveredT1,T3,T4
1CoveredT1,T4,T5

 LINE       710
 EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
             ---------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4

 LINE       710
 SUB-EXPRESSION (reg_re || reg_we)
                 ---1--    ---2--
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT3,T32,T13
10CoveredT1,T4,T5

 LINE       714
 EXPRESSION 
 Number  Term
      1  reg_we & 
      2  ((addr_hit[0] & ((|(4'b1 & (~reg_be))))) | (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | (addr_hit[2] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[3] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[4] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[5] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[6] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[7] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[8] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[9] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[10] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[11] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[12] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[13] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[14] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[15] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[16] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[17] & ((|(4'b1111 & (~reg_be)))))))
-1--2-StatusTests
01CoveredT1,T3,T4
10CoveredT3,T32,T13
11CoveredT13,T15,T16

 LINE       714
 SUB-EXPRESSION 
 Number  Term
      1  (addr_hit[0] & ((|(4'b1 & (~reg_be))))) | 
      2  (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | 
      3  (addr_hit[2] & ((|(4'b1111 & (~reg_be))))) | 
      4  (addr_hit[3] & ((|(4'b1111 & (~reg_be))))) | 
      5  (addr_hit[4] & ((|(4'b1111 & (~reg_be))))) | 
      6  (addr_hit[5] & ((|(4'b1111 & (~reg_be))))) | 
      7  (addr_hit[6] & ((|(4'b1111 & (~reg_be))))) | 
      8  (addr_hit[7] & ((|(4'b1111 & (~reg_be))))) | 
      9  (addr_hit[8] & ((|(4'b1111 & (~reg_be))))) | 
     10  (addr_hit[9] & ((|(4'b1111 & (~reg_be))))) | 
     11  (addr_hit[10] & ((|(4'b1111 & (~reg_be))))) | 
     12  (addr_hit[11] & ((|(4'b1111 & (~reg_be))))) | 
     13  (addr_hit[12] & ((|(4'b1111 & (~reg_be))))) | 
     14  (addr_hit[13] & ((|(4'b1111 & (~reg_be))))) | 
     15  (addr_hit[14] & ((|(4'b1111 & (~reg_be))))) | 
     16  (addr_hit[15] & ((|(4'b1111 & (~reg_be))))) | 
     17  (addr_hit[16] & ((|(4'b1111 & (~reg_be))))) | 
     18  (addr_hit[17] & ((|(4'b1111 & (~reg_be))))))
-1--2--3--4--5--6--7--8--9--10--11--12--13--14--15--16--17--18-StatusTests
000000000000000000CoveredT1,T3,T4
000000000000000001CoveredT1,T5,T8
000000000000000010CoveredT1,T5,T8
000000000000000100CoveredT1,T4,T5
000000000000001000CoveredT5,T8,T19
000000000000010000CoveredT1,T3,T4
000000000000100000CoveredT1,T4,T5
000000000001000000CoveredT1,T4,T5
000000000010000000CoveredT1,T4,T5
000000000100000000CoveredT1,T3,T5
000000001000000000CoveredT1,T4,T5
000000010000000000CoveredT1,T3,T5
000000100000000000CoveredT1,T5,T19
000001000000000000CoveredT1,T4,T5
000010000000000000CoveredT4,T8,T13
000100000000000000CoveredT1,T4,T5
001000000000000000CoveredT1,T5,T8
010000000000000000CoveredT9,T10,T27
100000000000000000CoveredT19,T13,T29

 LINE       714
 SUB-EXPRESSION (addr_hit[0] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T3,T4
10CoveredT3,T32,T19
11CoveredT19,T13,T29

 LINE       714
 SUB-EXPRESSION (addr_hit[1] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T3,T4
10CoveredT7,T10,T27
11CoveredT9,T10,T27

 LINE       714
 SUB-EXPRESSION (addr_hit[2] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T3,T4
10CoveredT1,T4,T5
11CoveredT1,T5,T8

 LINE       714
 SUB-EXPRESSION (addr_hit[3] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T3,T4
10CoveredT4,T5,T8
11CoveredT1,T4,T5

 LINE       714
 SUB-EXPRESSION (addr_hit[4] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T3,T4
10CoveredT1,T4,T5
11CoveredT4,T8,T13

 LINE       714
 SUB-EXPRESSION (addr_hit[5] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T3,T4
10CoveredT1,T4,T5
11CoveredT1,T4,T5

 LINE       714
 SUB-EXPRESSION (addr_hit[6] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T3,T4
10CoveredT1,T4,T5
11CoveredT1,T5,T19

 LINE       714
 SUB-EXPRESSION (addr_hit[7] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T3,T4
10CoveredT4,T8,T13
11CoveredT1,T3,T5

 LINE       714
 SUB-EXPRESSION (addr_hit[8] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T3,T4
10CoveredT1,T4,T5
11CoveredT1,T4,T5

 LINE       714
 SUB-EXPRESSION (addr_hit[9] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T3,T4
10CoveredT4,T5,T8
11CoveredT1,T3,T5

 LINE       714
 SUB-EXPRESSION (addr_hit[10] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T3,T4
10CoveredT1,T4,T5
11CoveredT1,T4,T5

 LINE       714
 SUB-EXPRESSION (addr_hit[11] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T3,T4
10CoveredT1,T4,T5
11CoveredT1,T4,T5

 LINE       714
 SUB-EXPRESSION (addr_hit[12] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T3,T4
10CoveredT1,T4,T5
11CoveredT1,T4,T5

 LINE       714
 SUB-EXPRESSION (addr_hit[13] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T3,T4
10CoveredT1,T4,T5
11CoveredT1,T3,T4

 LINE       714
 SUB-EXPRESSION (addr_hit[14] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T3,T4
10CoveredT1,T4,T5
11CoveredT5,T8,T19

 LINE       714
 SUB-EXPRESSION (addr_hit[15] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T3,T4
10CoveredT4,T5,T8
11CoveredT1,T4,T5

 LINE       714
 SUB-EXPRESSION (addr_hit[16] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T3,T4
10CoveredT1,T4,T5
11CoveredT1,T5,T8

 LINE       714
 SUB-EXPRESSION (addr_hit[17] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T3,T4
10CoveredT1,T4,T5
11CoveredT1,T5,T8

 LINE       736
 EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT64,T65,T66
101CoveredT3,T32,T19
110CoveredT13,T15,T16
111CoveredT3,T32,T33

Branch Coverage for Module : rom_ctrl_regs_reg_top
Line No.TotalCoveredPercent
Branches 24 24 100.00
TERNARY 710 2 2 100.00
IF 68 3 3 100.00
CASE 766 19 19 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl_regs_reg_top.sv' or '../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl_regs_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 710 ((reg_re || reg_we)) ?

Branches:
-1-StatusTests
1 Covered T1,T3,T4
0 Covered T1,T2,T3


LineNo. Expression -1-: 68 if ((!rst_ni)) -2-: 70 if ((intg_err || reg_we_err))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T23,T30,T31
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 766 case (1'b1)

Branches:
-1-StatusTests
addr_hit[0] Covered T1,T2,T3
addr_hit[1] Covered T1,T2,T4
addr_hit[2] Covered T1,T2,T4
addr_hit[3] Covered T1,T2,T4
addr_hit[4] Covered T1,T2,T4
addr_hit[5] Covered T1,T2,T4
addr_hit[6] Covered T1,T2,T4
addr_hit[7] Covered T1,T2,T3
addr_hit[8] Covered T1,T2,T4
addr_hit[9] Covered T1,T2,T3
addr_hit[10] Covered T1,T2,T4
addr_hit[11] Covered T1,T2,T4
addr_hit[12] Covered T1,T2,T4
addr_hit[13] Covered T1,T2,T3
addr_hit[14] Covered T1,T2,T4
addr_hit[15] Covered T1,T2,T4
addr_hit[16] Covered T1,T2,T4
addr_hit[17] Covered T1,T2,T4
default Covered T1,T2,T4


Assert Coverage for Module : rom_ctrl_regs_reg_top
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
en2addrHit 203469446 118455 0 0
reAfterRv 203469446 118455 0 0
rePulse 203469446 33868 0 0
wePulse 203469446 84587 0 0


en2addrHit
NameAttemptsReal SuccessesFailuresIncomplete
Total 203469446 118455 0 0
T1 312420 32 0 0
T2 42017 0 0 0
T3 74470 3 0 0
T4 382263 32 0 0
T5 383385 64 0 0
T6 193229 0 0 0
T7 204798 1 0 0
T8 447089 64 0 0
T9 16632 1 0 0
T10 550127 19 0 0
T27 0 20 0 0
T32 0 6 0 0

reAfterRv
NameAttemptsReal SuccessesFailuresIncomplete
Total 203469446 118455 0 0
T1 312420 32 0 0
T2 42017 0 0 0
T3 74470 3 0 0
T4 382263 32 0 0
T5 383385 64 0 0
T6 193229 0 0 0
T7 204798 1 0 0
T8 447089 64 0 0
T9 16632 1 0 0
T10 550127 19 0 0
T27 0 20 0 0
T32 0 6 0 0

rePulse
NameAttemptsReal SuccessesFailuresIncomplete
Total 203469446 33868 0 0
T1 312420 32 0 0
T2 42017 0 0 0
T3 74470 0 0 0
T4 382263 32 0 0
T5 383385 64 0 0
T6 193229 0 0 0
T7 204798 1 0 0
T8 447089 64 0 0
T9 16632 1 0 0
T10 550127 19 0 0
T19 0 20 0 0
T20 0 25 0 0
T27 0 20 0 0

wePulse
NameAttemptsReal SuccessesFailuresIncomplete
Total 203469446 84587 0 0
T3 74470 3 0 0
T4 382263 0 0 0
T5 383385 0 0 0
T6 193229 0 0 0
T7 204798 0 0 0
T8 447089 0 0 0
T9 16632 0 0 0
T10 550127 0 0 0
T13 0 7944 0 0
T15 0 5870 0 0
T16 0 4033 0 0
T27 543922 0 0 0
T32 73999 6 0 0
T33 0 13 0 0
T57 0 10 0 0
T58 0 12 0 0
T59 0 5 0 0
T60 0 8 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%