Unified Coverage Report :: Module :: rom_ctrl

Module : rom_ctrl

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.98	100.00	98.28	97.33		100.00	79.31

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	94.98	100.00	98.28	97.33		100.00	79.31

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.98	100.00	98.28	97.33		100.00	79.31

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.40	96.97	92.80	97.88	100.00	98.68	98.04

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_alert_tx[0].u_alert_sender	100.00			100.00
gen_fsm_scramble_enabled.u_checker_fsm	96.36	100.00	97.22	90.00	100.00	100.00	90.91
gen_rom_scramble_enabled.u_rom	97.06	88.24		100.00		100.00	100.00
regs_tlul_assert_device	100.00	100.00				100.00	100.00
rom_ctrl_regs_csr_assert	100.00						100.00
rom_tlul_assert_device	99.30	100.00				100.00	97.90
u_mux	95.24	100.00	85.71			100.00
u_reg_regs	99.72	99.41	99.21	100.00		100.00	100.00
u_tl_adapter_rom	93.77	91.56	83.06	99.07		95.18	100.00
u_tl_rom_h2d_buf	100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rom_ctrl

	Line No.	Total	Covered	Percent
TOTAL		65	65	100.00
CONT_ASSIGN	120	1	1	100.00
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	127	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	207	1	1	100.00
CONT_ASSIGN	253	1	1	100.00
CONT_ASSIGN	308	1	1	100.00
CONT_ASSIGN	409	1	1	100.00
CONT_ASSIGN	409	1	1	100.00
CONT_ASSIGN	409	1	1	100.00
CONT_ASSIGN	409	1	1	100.00
CONT_ASSIGN	409	1	1	100.00
CONT_ASSIGN	409	1	1	100.00
CONT_ASSIGN	409	1	1	100.00
CONT_ASSIGN	409	1	1	100.00
CONT_ASSIGN	410	1	1	100.00
CONT_ASSIGN	410	1	1	100.00
CONT_ASSIGN	410	1	1	100.00
CONT_ASSIGN	410	1	1	100.00
CONT_ASSIGN	410	1	1	100.00
CONT_ASSIGN	410	1	1	100.00
CONT_ASSIGN	410	1	1	100.00
CONT_ASSIGN	410	1	1	100.00
CONT_ASSIGN	412	1	1	100.00
CONT_ASSIGN	412	1	1	100.00
CONT_ASSIGN	412	1	1	100.00
CONT_ASSIGN	412	1	1	100.00
CONT_ASSIGN	412	1	1	100.00
CONT_ASSIGN	412	1	1	100.00
CONT_ASSIGN	412	1	1	100.00
CONT_ASSIGN	412	1	1	100.00
CONT_ASSIGN	413	1	1	100.00
CONT_ASSIGN	413	1	1	100.00
CONT_ASSIGN	413	1	1	100.00
CONT_ASSIGN	413	1	1	100.00
CONT_ASSIGN	413	1	1	100.00
CONT_ASSIGN	413	1	1	100.00
CONT_ASSIGN	413	1	1	100.00
CONT_ASSIGN	413	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	422	1	1	100.00
CONT_ASSIGN	425	1	1	100.00
CONT_ASSIGN	426	1	1	100.00
CONT_ASSIGN	427	1	1	100.00
CONT_ASSIGN	428	1	1	100.00
CONT_ASSIGN	433	1	1	100.00
CONT_ASSIGN	437	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv' or '../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
120	1	1
125	1	1
126	1	1
127	1	1
128	1	1
131	1	1
207	1	1
253	1	1
308	1	1
409	8	8
410	8	8
412	8	8
413	8	8
415	8	8
416	8	8
420	1	1
422	1	1
425	1	1
426	1	1
427	1	1
428	1	1
433	1	1
437	1	1

---

Cond Coverage for Module : rom_ctrl

	Total	Covered	Percent
Conditions	58	57	98.28
Logical	58	57	98.28
Non-Logical	0	0
Event	0	0

 LINE       207
 EXPRESSION (rom_tl_i.a_valid ? rom_tl_i.a_address[2+:RomIndexWidth] : '0)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       253
 EXPRESSION (bus_rom_rvalid_raw & ((!internal_alert)))
             ---------1--------   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T9,T28
1	1	Covered	T1,T3,T4

 LINE       413
 EXPRESSION (exp_digest_de && (0 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       413
 SUB-EXPRESSION (0 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       413
 EXPRESSION (exp_digest_de && (1 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       413
 SUB-EXPRESSION (1 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       413
 EXPRESSION (exp_digest_de && (2 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       413
 SUB-EXPRESSION (2 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       413
 EXPRESSION (exp_digest_de && (3 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       413
 SUB-EXPRESSION (3 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       413
 EXPRESSION (exp_digest_de && (4 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       413
 SUB-EXPRESSION (4 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       413
 EXPRESSION (exp_digest_de && (5 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       413
 SUB-EXPRESSION (5 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       413
 EXPRESSION (exp_digest_de && (6 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       413
 SUB-EXPRESSION (6 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       413
 EXPRESSION (exp_digest_de && (7 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       413
 SUB-EXPRESSION (7 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION (rom_integrity_error | reg_integrity_error)
             ---------1---------   ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T30,T31,T32
1	0	Not Covered

 LINE       422
 EXPRESSION (checker_alert | mux_alert)
             ------1------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T9,T28
1	0	Covered	T2,T3,T5

 LINE       433
 EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
             ---------1---------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T7,T33,T34
1	0	Covered	T1,T3,T4
1	1	Covered	T7,T34,T35

 LINE       437
 EXPRESSION (bus_integrity_error | checker_alert | mux_alert)
             ---------1---------   ------2------   ----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T3,T9,T28
0	1	0	Covered	T2,T3,T5
1	0	0	Covered	T30,T31,T32

---

Toggle Coverage for Module : rom_ctrl

	Total	Covered	Percent
Totals	61	56	91.80
Total Bits	2882	2805	97.33
Total Bits 0->1	1441	1402	97.29
Total Bits 1->0	1441	1403	97.36

Ports	61	56	91.80
Port Bits	2882	2805	97.33
Port Bits 0->1	1441	1402	97.29
Port Bits 1->0	1441	1403	97.36

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rom_cfg_i.cfg[3:0]	No	No		No		INPUT
rom_cfg_i.cfg_en	No	No		No		INPUT
rom_tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rom_tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T4,T6	Yes	T1,T4,T6	INPUT
rom_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
rom_tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T6,T7	Yes	T1,T6,T8	INPUT
rom_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
rom_tl_i.a_data[31:0]	Yes	Yes	T1,T4,T6	Yes	T1,T4,T6	INPUT
rom_tl_i.a_mask[3:0]	Yes	Yes	T1,T4,T6	Yes	T1,T4,T6	INPUT
rom_tl_i.a_address[31:0]	Yes	Yes	T1,T4,T6	Yes	T1,T4,T6	INPUT
rom_tl_i.a_source[7:0]	Yes	Yes	T1,T4,T6	Yes	T1,T4,T6	INPUT
rom_tl_i.a_size[1:0]	Yes	Yes	T1,T4,T6	Yes	T1,T4,T6	INPUT
rom_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
rom_tl_i.a_opcode[2:0]	Yes	Yes	T1,T6,T8	Yes	T1,T6,T7	INPUT
rom_tl_i.a_valid	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
rom_tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
rom_tl_o.d_error	Yes	Yes	T1,T11,T12	Yes	T1,T11,T12	OUTPUT
rom_tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
rom_tl_o.d_user.rsp_intg[5:0]	Yes	Yes	T1,*T3,*T4	Yes	T1,T3,T4	OUTPUT
rom_tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
rom_tl_o.d_data[31:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
rom_tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
rom_tl_o.d_source[7:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
rom_tl_o.d_size[1:0]	Yes	Yes	T1,T4,T6	Yes	T1,T4,T6	OUTPUT
rom_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
rom_tl_o.d_opcode[0]	Yes	Yes	*T1,*T11,*T12	Yes	T1,T11,T12	OUTPUT
rom_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
rom_tl_o.d_valid	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
regs_tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
regs_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
regs_tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T8,T36	Yes	T1,T8,T33	INPUT
regs_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_data[31:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
regs_tl_i.a_mask[3:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
regs_tl_i.a_address[31:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
regs_tl_i.a_source[7:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
regs_tl_i.a_size[1:0]	Yes	Yes	T1,T4,T6	Yes	T1,T4,T6	INPUT
regs_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_opcode[2:0]	Yes	Yes	T1,T7,T8	Yes	T1,T7,T8	INPUT
regs_tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
regs_tl_o.d_error	Yes	Yes	T1,T11,T12	Yes	T1,T11,T12	OUTPUT
regs_tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
regs_tl_o.d_user.rsp_intg[5:0]	Yes	Yes	T1,*T3,*T4	Yes	T1,T3,T4	OUTPUT
regs_tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
regs_tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
regs_tl_o.d_size[1:0]	Yes	Yes	T1,T4,T6	Yes	T1,T4,T6	OUTPUT
regs_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
regs_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T2,T3,T5	Yes	T2,T3,T5	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T2,T3,T5	Yes	T2,T3,T5	OUTPUT
pwrmgr_data_o.good[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
pwrmgr_data_o.done[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T3,T4	OUTPUT
keymgr_data_o.valid	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	OUTPUT
keymgr_data_o.data[255:0]	Yes	Yes	T3,T4,T8	Yes	T3,T4,T6	OUTPUT
kmac_data_i.error	No	Yes	T2,T5,T10	No		INPUT
kmac_data_i.digest_share1[383:0]	Yes	Yes	T1,T3,T8	Yes	T1,T2,T3	INPUT
kmac_data_i.digest_share0[383:0]	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
kmac_data_i.done	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
kmac_data_i.ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
kmac_data_o.last	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
kmac_data_o.strb[7:0]	No	No		No		OUTPUT
kmac_data_o.data[38:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
kmac_data_o.data[63:39]	No	No		No		OUTPUT
kmac_data_o.valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Module : rom_ctrl

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
TERNARY	207	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv' or '../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	207	(rom_tl_i.a_valid) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Module : rom_ctrl

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	29	29	100.00	23	79.31
Cover properties	0	0		0
Cover sequences	0	0		0
Total	29	29	100.00	23	79.31

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxOKnown_A	181200382	181025167	0	0
BusRomIndicesMatch_A	181189491	181020611	0	0
FpvSecCmFifoRptrCheck_A	181200382	0	0	0
FpvSecCmFifoWptrCheck_A	181200382	0	0	0
FpvSecCmRegWeOnehotCheck_A	181200382	80	0	0
KeymgrDataODataKnown_A	181200382	53981718	0	0
KeymgrDataODataKnown_AKnownEnable	181200382	181025167	0	0
KeymgrDataOValidKnown_A	181200382	181025167	0	0
KeymgrValidChk_A	181200382	0	0	321
KmacDataODataKnown_A	181200382	126928243	0	0
KmacDataODataKnown_AKnownEnable	181200382	181025167	0	0
KmacDataOValidKnown_A	181200382	181025167	0	0
PwrmgrDataChk_A	181200382	0	0	321
PwrmgrDataOKnown_A	181200382	181025167	0	0
RegsTlOAReadyKnown_A	181200382	181025167	0	0
RegsTlODDataKnown_A	181200382	5972008	0	0
RegsTlODDataKnown_AKnownEnable	181200382	181025167	0	0
RegsTlODValidKnown_A	181200382	181025167	0	0
RomTlOAReadyKnown_A	181200382	181025167	0	0
RomTlODDataKnown_A	181200382	10170553	0	0
RomTlODDataKnown_AKnownEnable	181200382	181025167	0	0
RomTlODValidKnown_A	181200382	181025167	0	0
StabilityChkKmac_A	181200382	126925819	0	0
StabilityChkkeymgr_A	181200382	53980558	0	0
TlAccessChk_A	181200382	127043449	0	0
gen_asserts_with_scrambling.FpvSecCmCheckerFsmAlert_A	181200382	80	0	0
gen_asserts_with_scrambling.FpvSecCmCompareAddrCtrCheck_A	181200382	0	0	0
gen_asserts_with_scrambling.FpvSecCmCompareFsmAlert_A	181200382	532	0	0
gen_fsm_scramble_enabled_asserts.BusLocalEscChk_A	181200382	0	0	0

AlertTxOKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181200382	181025167	0	0
T1	328720	328708	0	0
T2	16700	16524	0	0
T3	151735	149311	0	0
T4	222578	222461	0	0
T5	260939	260810	0	0
T6	17722	17564	0	0
T7	123427	123335	0	0
T8	137392	136863	0	0
T9	340402	340084	0	0
T10	204826	204680	0	0

BusRomIndicesMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181189491	181020611	0	0
T1	328720	328708	0	0
T2	16700	16524	0	0
T3	151565	149241	0	0
T4	222578	222461	0	0
T5	260939	260810	0	0
T6	17722	17564	0	0
T7	123427	123335	0	0
T8	137392	136863	0	0
T9	340374	340079	0	0
T10	204826	204680	0	0

FpvSecCmFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181200382	0	0	0

FpvSecCmFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181200382	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181200382	80	0	0
T21	16676	0	0	0
T30	130832	10	0	0
T31	0	20	0	0
T32	0	10	0	0
T37	0	20	0	0
T38	0	20	0	0
T39	129007	0	0	0
T40	230620	0	0	0
T41	395191	0	0	0
T42	109264	0	0	0
T43	142873	0	0	0
T44	16646	0	0	0
T45	201480	0	0	0
T46	8375	0	0	0

KeymgrDataODataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181200382	53981718	0	0
T1	328720	323785	0	0
T2	16700	93	0	0
T3	151735	12569	0	0
T4	222578	1555	0	0
T5	260939	208	0	0
T6	17722	1154	0	0
T7	123427	67	0	0
T8	137392	4641	0	0
T9	340402	9099	0	0
T10	204826	134	0	0

KeymgrDataODataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	181200382	181025167	0	0
T1	328720	328708	0	0
T2	16700	16524	0	0
T3	151735	149311	0	0
T4	222578	222461	0	0
T5	260939	260810	0	0
T6	17722	17564	0	0
T7	123427	123335	0	0
T8	137392	136863	0	0
T9	340402	340084	0	0
T10	204826	204680	0	0

KeymgrDataOValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181200382	181025167	0	0
T1	328720	328708	0	0
T2	16700	16524	0	0
T3	151735	149311	0	0
T4	222578	222461	0	0
T5	260939	260810	0	0
T6	17722	17564	0	0
T7	123427	123335	0	0
T8	137392	136863	0	0
T9	340402	340084	0	0
T10	204826	204680	0	0

KeymgrValidChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181200382	0	0	321

KmacDataODataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181200382	126928243	0	0
T1	328720	49104	0	0
T2	16700	16368	0	0
T3	151735	135759	0	0
T4	222578	220765	0	0
T5	260939	260438	0	0
T6	17722	16368	0	0
T7	123427	123216	0	0
T8	137392	131947	0	0
T9	340402	338983	0	0
T10	204826	204340	0	0

KmacDataODataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	181200382	181025167	0	0
T1	328720	328708	0	0
T2	16700	16524	0	0
T3	151735	149311	0	0
T4	222578	222461	0	0
T5	260939	260810	0	0
T6	17722	17564	0	0
T7	123427	123335	0	0
T8	137392	136863	0	0
T9	340402	340084	0	0
T10	204826	204680	0	0

KmacDataOValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181200382	181025167	0	0
T1	328720	328708	0	0
T2	16700	16524	0	0
T3	151735	149311	0	0
T4	222578	222461	0	0
T5	260939	260810	0	0
T6	17722	17564	0	0
T7	123427	123335	0	0
T8	137392	136863	0	0
T9	340402	340084	0	0
T10	204826	204680	0	0

PwrmgrDataChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181200382	0	0	321

PwrmgrDataOKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181200382	181025167	0	0
T1	328720	328708	0	0
T2	16700	16524	0	0
T3	151735	149311	0	0
T4	222578	222461	0	0
T5	260939	260810	0	0
T6	17722	17564	0	0
T7	123427	123335	0	0
T8	137392	136863	0	0
T9	340402	340084	0	0
T10	204826	204680	0	0

RegsTlOAReadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181200382	181025167	0	0
T1	328720	328708	0	0
T2	16700	16524	0	0
T3	151735	149311	0	0
T4	222578	222461	0	0
T5	260939	260810	0	0
T6	17722	17564	0	0
T7	123427	123335	0	0
T8	137392	136863	0	0
T9	340402	340084	0	0
T10	204826	204680	0	0

RegsTlODDataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181200382	5972008	0	0
T1	328720	276549	0	0
T2	16700	1	0	0
T3	151735	112	0	0
T4	222578	157	0	0
T5	260939	3	0	0
T6	17722	32	0	0
T7	123427	18	0	0
T8	137392	221	0	0
T9	340402	33	0	0
T10	204826	1	0	0

RegsTlODDataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	181200382	181025167	0	0
T1	328720	328708	0	0
T2	16700	16524	0	0
T3	151735	149311	0	0
T4	222578	222461	0	0
T5	260939	260810	0	0
T6	17722	17564	0	0
T7	123427	123335	0	0
T8	137392	136863	0	0
T9	340402	340084	0	0
T10	204826	204680	0	0

RegsTlODValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181200382	181025167	0	0
T1	328720	328708	0	0
T2	16700	16524	0	0
T3	151735	149311	0	0
T4	222578	222461	0	0
T5	260939	260810	0	0
T6	17722	17564	0	0
T7	123427	123335	0	0
T8	137392	136863	0	0
T9	340402	340084	0	0
T10	204826	204680	0	0

RomTlOAReadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181200382	181025167	0	0
T1	328720	328708	0	0
T2	16700	16524	0	0
T3	151735	149311	0	0
T4	222578	222461	0	0
T5	260939	260810	0	0
T6	17722	17564	0	0
T7	123427	123335	0	0
T8	137392	136863	0	0
T9	340402	340084	0	0
T10	204826	204680	0	0

RomTlODDataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181200382	10170553	0	0
T1	328720	348028	0	0
T2	16700	0	0	0
T3	151735	17	0	0
T4	222578	417	0	0
T5	260939	0	0	0
T6	17722	75	0	0
T7	123427	0	0	0
T8	137392	115	0	0
T9	340402	9	0	0
T10	204826	0	0	0
T16	0	856	0	0
T17	0	264	0	0
T18	0	60	0	0
T19	0	389	0	0

RomTlODDataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	181200382	181025167	0	0
T1	328720	328708	0	0
T2	16700	16524	0	0
T3	151735	149311	0	0
T4	222578	222461	0	0
T5	260939	260810	0	0
T6	17722	17564	0	0
T7	123427	123335	0	0
T8	137392	136863	0	0
T9	340402	340084	0	0
T10	204826	204680	0	0

RomTlODValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181200382	181025167	0	0
T1	328720	328708	0	0
T2	16700	16524	0	0
T3	151735	149311	0	0
T4	222578	222461	0	0
T5	260939	260810	0	0
T6	17722	17564	0	0
T7	123427	123335	0	0
T8	137392	136863	0	0
T9	340402	340084	0	0
T10	204826	204680	0	0

StabilityChkKmac_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181200382	126925819	0	0
T1	328720	49098	0	0
T2	16700	16366	0	0
T3	151735	135728	0	0
T4	222578	220763	0	0
T5	260939	260436	0	0
T6	17722	16366	0	0
T7	123427	123215	0	0
T8	137392	131940	0	0
T9	340402	338979	0	0
T10	204826	204338	0	0

StabilityChkkeymgr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181200382	53980558	0	0
T1	328720	323784	0	0
T2	16700	92	0	0
T3	151735	12556	0	0
T4	222578	1553	0	0
T5	260939	207	0	0
T6	17722	1152	0	0
T7	123427	66	0	0
T8	137392	4637	0	0
T9	340402	9087	0	0
T10	204826	133	0	0

TlAccessChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181200382	127043449	0	0
T1	328720	49230	0	0
T2	16700	16431	0	0
T3	151735	136742	0	0
T4	222578	220906	0	0
T5	260939	260602	0	0
T6	17722	16410	0	0
T7	123427	123268	0	0
T8	137392	132222	0	0
T9	340402	339174	0	0
T10	204826	204546	0	0

gen_asserts_with_scrambling.FpvSecCmCheckerFsmAlert_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181200382	80	0	0
T21	16676	0	0	0
T30	130832	10	0	0
T31	0	20	0	0
T32	0	10	0	0
T37	0	20	0	0
T38	0	20	0	0
T39	129007	0	0	0
T40	230620	0	0	0
T41	395191	0	0	0
T42	109264	0	0	0
T43	142873	0	0	0
T44	16646	0	0	0
T45	201480	0	0	0
T46	8375	0	0	0

gen_asserts_with_scrambling.FpvSecCmCompareAddrCtrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181200382	0	0	0

gen_asserts_with_scrambling.FpvSecCmCompareFsmAlert_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181200382	532	0	0
T3	151735	5	0	0
T4	222578	0	0	0
T5	260939	0	0	0
T6	17722	0	0	0
T7	123427	0	0	0
T8	137392	0	0	0
T9	340402	21	0	0
T10	204826	0	0	0
T16	28656	0	0	0
T17	99808	0	0	0
T22	0	20	0	0
T27	0	15	0	0
T28	0	10	0	0
T29	0	11	0	0
T30	0	10	0	0
T47	0	10	0	0
T48	0	5	0	0
T49	0	10	0	0

gen_fsm_scramble_enabled_asserts.BusLocalEscChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181200382	0	0	0