Module Definition
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Module : rom_ctrl_regs_csr_assert_fpv
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rom_ctrl_csr_assert_0/rom_ctrl_regs_csr_assert_fpv.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.rom_ctrl_regs_csr_assert 100.00 100.00



Module Instance : tb.dut.rom_ctrl_regs_csr_assert

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.98 100.00 98.28 97.33 100.00 79.31 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Assert Coverage for Module : rom_ctrl_regs_csr_assert_fpv
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
TlulOOBAddrErr_A 205450616 1861206 0 0


TlulOOBAddrErr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 205450616 1861206 0 0
T1 328720 155611 0 0
T2 16700 0 0 0
T3 151735 0 0 0
T4 222578 0 0 0
T5 260939 0 0 0
T6 17722 0 0 0
T7 123427 0 0 0
T8 137392 0 0 0
T9 340402 0 0 0
T10 204826 0 0 0
T11 0 40508 0 0
T12 0 170077 0 0
T13 0 202508 0 0
T51 0 145466 0 0
T52 0 127919 0 0
T53 0 86529 0 0
T54 0 76530 0 0
T55 0 63790 0 0
T56 0 131080 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%