Toggle Coverage for Module :
prim_prince
| Total | Covered | Percent |
Totals |
6 |
6 |
100.00 |
Total Bits |
164 |
164 |
100.00 |
Total Bits 0->1 |
82 |
82 |
100.00 |
Total Bits 1->0 |
82 |
82 |
100.00 |
| | | |
Ports |
6 |
6 |
100.00 |
Port Bits |
164 |
164 |
100.00 |
Port Bits 0->1 |
82 |
82 |
100.00 |
Port Bits 1->0 |
82 |
82 |
100.00 |
Port Details
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
rst_ni |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
valid_i |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
data_i[13:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
data_i[63:14] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
key_i[127:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
dec_i |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
valid_o |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
data_o[63:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |