Unified Coverage Report :: Module :: rom_ctrl

Module : rom_ctrl

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.98	100.00	98.28	97.33		100.00	79.31

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	94.98	100.00	98.28	97.33		100.00	79.31

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.98	100.00	98.28	97.33		100.00	79.31

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.50	96.97	93.25	97.88	100.00	99.01	97.89

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_alert_tx[0].u_alert_sender	100.00			100.00
gen_fsm_scramble_enabled.u_checker_fsm	96.36	100.00	97.22	90.00	100.00	100.00	90.91
gen_rom_scramble_enabled.u_rom	97.06	88.24		100.00		100.00	100.00
regs_tlul_assert_device	100.00	100.00				100.00	100.00
rom_ctrl_regs_csr_assert	100.00						100.00
rom_tlul_assert_device	99.18	100.00				100.00	97.55
u_mux	95.24	100.00	85.71			100.00
u_reg_regs	99.72	99.41	99.21	100.00		100.00	100.00
u_tl_adapter_rom	94.26	91.56	84.30	99.07		96.39	100.00
u_tl_rom_h2d_buf	100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rom_ctrl

	Line No.	Total	Covered	Percent
TOTAL		65	65	100.00
CONT_ASSIGN	120	1	1	100.00
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	127	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	207	1	1	100.00
CONT_ASSIGN	253	1	1	100.00
CONT_ASSIGN	308	1	1	100.00
CONT_ASSIGN	409	1	1	100.00
CONT_ASSIGN	409	1	1	100.00
CONT_ASSIGN	409	1	1	100.00
CONT_ASSIGN	409	1	1	100.00
CONT_ASSIGN	409	1	1	100.00
CONT_ASSIGN	409	1	1	100.00
CONT_ASSIGN	409	1	1	100.00
CONT_ASSIGN	409	1	1	100.00
CONT_ASSIGN	410	1	1	100.00
CONT_ASSIGN	410	1	1	100.00
CONT_ASSIGN	410	1	1	100.00
CONT_ASSIGN	410	1	1	100.00
CONT_ASSIGN	410	1	1	100.00
CONT_ASSIGN	410	1	1	100.00
CONT_ASSIGN	410	1	1	100.00
CONT_ASSIGN	410	1	1	100.00
CONT_ASSIGN	412	1	1	100.00
CONT_ASSIGN	412	1	1	100.00
CONT_ASSIGN	412	1	1	100.00
CONT_ASSIGN	412	1	1	100.00
CONT_ASSIGN	412	1	1	100.00
CONT_ASSIGN	412	1	1	100.00
CONT_ASSIGN	412	1	1	100.00
CONT_ASSIGN	412	1	1	100.00
CONT_ASSIGN	413	1	1	100.00
CONT_ASSIGN	413	1	1	100.00
CONT_ASSIGN	413	1	1	100.00
CONT_ASSIGN	413	1	1	100.00
CONT_ASSIGN	413	1	1	100.00
CONT_ASSIGN	413	1	1	100.00
CONT_ASSIGN	413	1	1	100.00
CONT_ASSIGN	413	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	422	1	1	100.00
CONT_ASSIGN	425	1	1	100.00
CONT_ASSIGN	426	1	1	100.00
CONT_ASSIGN	427	1	1	100.00
CONT_ASSIGN	428	1	1	100.00
CONT_ASSIGN	433	1	1	100.00
CONT_ASSIGN	437	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv' or '../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
120	1	1
125	1	1
126	1	1
127	1	1
128	1	1
131	1	1
207	1	1
253	1	1
308	1	1
409	8	8
410	8	8
412	8	8
413	8	8
415	8	8
416	8	8
420	1	1
422	1	1
425	1	1
426	1	1
427	1	1
428	1	1
433	1	1
437	1	1

---

Cond Coverage for Module : rom_ctrl

	Total	Covered	Percent
Conditions	58	57	98.28
Logical	58	57	98.28
Non-Logical	0	0
Event	0	0

 LINE       207
 EXPRESSION (rom_tl_i.a_valid ? rom_tl_i.a_address[2+:RomIndexWidth] : '0)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       253
 EXPRESSION (bus_rom_rvalid_raw & ((!internal_alert)))
             ---------1--------   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T30
1	1	Covered	T1,T2,T3

 LINE       413
 EXPRESSION (exp_digest_de && (0 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       413
 SUB-EXPRESSION (0 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       413
 EXPRESSION (exp_digest_de && (1 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       413
 SUB-EXPRESSION (1 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       413
 EXPRESSION (exp_digest_de && (2 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       413
 SUB-EXPRESSION (2 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       413
 EXPRESSION (exp_digest_de && (3 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       413
 SUB-EXPRESSION (3 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       413
 EXPRESSION (exp_digest_de && (4 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       413
 SUB-EXPRESSION (4 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       413
 EXPRESSION (exp_digest_de && (5 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       413
 SUB-EXPRESSION (5 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       413
 EXPRESSION (exp_digest_de && (6 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       413
 SUB-EXPRESSION (6 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       413
 EXPRESSION (exp_digest_de && (7 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       413
 SUB-EXPRESSION (7 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION (rom_integrity_error | reg_integrity_error)
             ---------1---------   ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T35,T36
1	0	Not Covered

 LINE       422
 EXPRESSION (checker_alert | mux_alert)
             ------1------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T4,T30
1	0	Covered	T1,T4,T5

 LINE       433
 EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
             ---------1---------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T7,T10,T37
1	0	Covered	T1,T2,T3
1	1	Covered	T7,T10,T37

 LINE       437
 EXPRESSION (bus_integrity_error | checker_alert | mux_alert)
             ---------1---------   ------2------   ----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T1,T4,T30
0	1	0	Covered	T1,T4,T5
1	0	0	Covered	T5,T35,T36

---

Toggle Coverage for Module : rom_ctrl

	Total	Covered	Percent
Totals	61	56	91.80
Total Bits	2882	2805	97.33
Total Bits 0->1	1441	1402	97.29
Total Bits 1->0	1441	1403	97.36

Ports	61	56	91.80
Port Bits	2882	2805	97.33
Port Bits 0->1	1441	1402	97.29
Port Bits 1->0	1441	1403	97.36

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rom_cfg_i.cfg[3:0]	No	No		No		INPUT
rom_cfg_i.cfg_en	No	No		No		INPUT
rom_tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rom_tl_i.a_user.data_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
rom_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
rom_tl_i.a_user.instr_type[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
rom_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
rom_tl_i.a_data[31:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
rom_tl_i.a_mask[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
rom_tl_i.a_address[31:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
rom_tl_i.a_source[7:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
rom_tl_i.a_size[1:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
rom_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
rom_tl_i.a_opcode[2:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
rom_tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rom_tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
rom_tl_o.d_error	Yes	Yes	T2,T12,T13	Yes	T2,T12,T13	OUTPUT
rom_tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
rom_tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,T2,*T3	Yes	T1,T2,T3	OUTPUT
rom_tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
rom_tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
rom_tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
rom_tl_o.d_source[7:0]	Yes	Yes	T2,T3,T6	Yes	T2,T3,T6	OUTPUT
rom_tl_o.d_size[1:0]	Yes	Yes	T2,T3,T6	Yes	T2,T3,T6	OUTPUT
rom_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
rom_tl_o.d_opcode[0]	Yes	Yes	*T2,*T12,*T13	Yes	T2,T12,T13	OUTPUT
rom_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
rom_tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
regs_tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_user.instr_type[3:0]	Yes	Yes	T2,T37,T12	Yes	T2,T37,T12	INPUT
regs_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T2,T3,T4	INPUT
regs_tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_opcode[2:0]	Yes	Yes	T2,T7,T37	Yes	T2,T7,T37	INPUT
regs_tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
regs_tl_o.d_error	Yes	Yes	T2,T12,T13	Yes	T2,T12,T13	OUTPUT
regs_tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
regs_tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,T2,*T3	Yes	T1,T2,T3	OUTPUT
regs_tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
regs_tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
regs_tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
regs_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
regs_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
pwrmgr_data_o.good[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
pwrmgr_data_o.done[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
keymgr_data_o.valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
keymgr_data_o.data[255:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
kmac_data_i.error	No	Yes	T27,T20,T21	No		INPUT
kmac_data_i.digest_share1[383:0]	Yes	Yes	T1,T3,T4	Yes	T1,T2,T4	INPUT
kmac_data_i.digest_share0[383:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T4	INPUT
kmac_data_i.done	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
kmac_data_i.ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
kmac_data_o.last	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
kmac_data_o.strb[7:0]	No	No		No		OUTPUT
kmac_data_o.data[38:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
kmac_data_o.data[63:39]	No	No		No		OUTPUT
kmac_data_o.valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Module : rom_ctrl

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
TERNARY	207	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv' or '../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	207	(rom_tl_i.a_valid) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : rom_ctrl

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	29	29	100.00	23	79.31
Cover properties	0	0		0
Cover sequences	0	0		0
Total	29	29	100.00	23	79.31

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxOKnown_A	612230826	611875301	0	0
BusRomIndicesMatch_A	612207380	611863893	0	0
FpvSecCmFifoRptrCheck_A	612230826	0	0	0
FpvSecCmFifoWptrCheck_A	612230826	0	0	0
FpvSecCmRegWeOnehotCheck_A	612230826	140	0	0
KeymgrDataODataKnown_A	612230826	71838840	0	0
KeymgrDataODataKnown_AKnownEnable	612230826	611875301	0	0
KeymgrDataOValidKnown_A	612230826	611875301	0	0
KeymgrValidChk_A	612230826	0	0	628
KmacDataODataKnown_A	612230826	539791149	0	0
KmacDataODataKnown_AKnownEnable	612230826	611875301	0	0
KmacDataOValidKnown_A	612230826	611875301	0	0
PwrmgrDataChk_A	612230826	0	0	628
PwrmgrDataOKnown_A	612230826	611875301	0	0
RegsTlOAReadyKnown_A	612230826	611875301	0	0
RegsTlODDataKnown_A	612230826	8256171	0	0
RegsTlODDataKnown_AKnownEnable	612230826	611875301	0	0
RegsTlODValidKnown_A	612230826	611875301	0	0
RomTlOAReadyKnown_A	612230826	611875301	0	0
RomTlODDataKnown_A	612230826	17242599	0	0
RomTlODDataKnown_AKnownEnable	612230826	611875301	0	0
RomTlODValidKnown_A	612230826	611875301	0	0
StabilityChkKmac_A	612230826	539786345	0	0
StabilityChkkeymgr_A	612230826	71836599	0	0
TlAccessChk_A	612230826	540036461	0	0
gen_asserts_with_scrambling.FpvSecCmCheckerFsmAlert_A	612230826	140	0	0
gen_asserts_with_scrambling.FpvSecCmCompareAddrCtrCheck_A	612230826	0	0	0
gen_asserts_with_scrambling.FpvSecCmCompareFsmAlert_A	612230826	1078	0	0
gen_fsm_scramble_enabled_asserts.BusLocalEscChk_A	612230826	0	0	0

AlertTxOKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	612230826	611875301	0	0
T1	390374	390227	0	0
T2	229195	229183	0	0
T3	722867	722715	0	0
T4	335221	332488	0	0
T5	272170	267640	0	0
T6	191048	190948	0	0
T7	362836	362783	0	0
T8	34541	34352	0	0
T9	187637	187555	0	0
T10	392846	392749	0	0

BusRomIndicesMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	612207380	611863893	0	0
T1	390355	390213	0	0
T2	229195	229183	0	0
T3	722867	722715	0	0
T4	335221	332488	0	0
T5	272170	267640	0	0
T6	191048	190948	0	0
T7	362836	362783	0	0
T8	34541	34352	0	0
T9	187637	187555	0	0
T10	392846	392749	0	0

FpvSecCmFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	612230826	0	0	0

FpvSecCmFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	612230826	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	612230826	140	0	0
T5	272170	20	0	0
T6	191048	0	0	0
T7	362836	0	0	0
T8	34541	0	0	0
T9	187637	0	0	0
T10	392846	0	0	0
T11	773015	0	0	0
T18	113446	0	0	0
T19	492686	0	0	0
T35	0	10	0	0
T36	0	10	0	0
T37	328204	0	0	0
T38	0	10	0	0
T39	0	10	0	0
T40	0	20	0	0
T41	0	20	0	0
T42	0	10	0	0
T43	0	20	0	0
T44	0	10	0	0

KeymgrDataODataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	612230826	71838840	0	0
T1	390374	19340	0	0
T2	229195	219345	0	0
T3	722867	1418	0	0
T4	335221	10257	0	0
T5	272170	156	0	0
T6	191048	1291	0	0
T7	362836	107	0	0
T8	34541	1558	0	0
T9	187637	1055	0	0
T10	392846	287	0	0

KeymgrDataODataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	612230826	611875301	0	0
T1	390374	390227	0	0
T2	229195	229183	0	0
T3	722867	722715	0	0
T4	335221	332488	0	0
T5	272170	267640	0	0
T6	191048	190948	0	0
T7	362836	362783	0	0
T8	34541	34352	0	0
T9	187637	187555	0	0
T10	392846	392749	0	0

KeymgrDataOValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	612230826	611875301	0	0
T1	390374	390227	0	0
T2	229195	229183	0	0
T3	722867	722715	0	0
T4	335221	332488	0	0
T5	272170	267640	0	0
T6	191048	190948	0	0
T7	362836	362783	0	0
T8	34541	34352	0	0
T9	187637	187555	0	0
T10	392846	392749	0	0

KeymgrValidChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	612230826	0	0	628

KmacDataODataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	612230826	539791149	0	0
T1	390374	388197	0	0
T2	229195	98256	0	0
T3	722867	721181	0	0
T4	335221	320873	0	0
T5	272170	256093	0	0
T6	191048	189636	0	0
T7	362836	362655	0	0
T8	34541	32752	0	0
T9	187637	186443	0	0
T10	392846	392369	0	0

KmacDataODataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	612230826	611875301	0	0
T1	390374	390227	0	0
T2	229195	229183	0	0
T3	722867	722715	0	0
T4	335221	332488	0	0
T5	272170	267640	0	0
T6	191048	190948	0	0
T7	362836	362783	0	0
T8	34541	34352	0	0
T9	187637	187555	0	0
T10	392846	392749	0	0

KmacDataOValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	612230826	611875301	0	0
T1	390374	390227	0	0
T2	229195	229183	0	0
T3	722867	722715	0	0
T4	335221	332488	0	0
T5	272170	267640	0	0
T6	191048	190948	0	0
T7	362836	362783	0	0
T8	34541	34352	0	0
T9	187637	187555	0	0
T10	392846	392749	0	0

PwrmgrDataChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	612230826	0	0	628

PwrmgrDataOKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	612230826	611875301	0	0
T1	390374	390227	0	0
T2	229195	229183	0	0
T3	722867	722715	0	0
T4	335221	332488	0	0
T5	272170	267640	0	0
T6	191048	190948	0	0
T7	362836	362783	0	0
T8	34541	34352	0	0
T9	187637	187555	0	0
T10	392846	392749	0	0

RegsTlOAReadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	612230826	611875301	0	0
T1	390374	390227	0	0
T2	229195	229183	0	0
T3	722867	722715	0	0
T4	335221	332488	0	0
T5	272170	267640	0	0
T6	191048	190948	0	0
T7	362836	362783	0	0
T8	34541	34352	0	0
T9	187637	187555	0	0
T10	392846	392749	0	0

RegsTlODDataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	612230826	8256171	0	0
T1	390374	16	0	0
T2	229195	126704	0	0
T3	722867	131	0	0
T4	335221	32	0	0
T5	272170	86	0	0
T6	191048	0	0	0
T7	362836	64	0	0
T8	34541	32	0	0
T9	187637	0	0	0
T10	392846	33	0	0
T18	0	32	0	0
T37	0	26	0	0

RegsTlODDataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	612230826	611875301	0	0
T1	390374	390227	0	0
T2	229195	229183	0	0
T3	722867	722715	0	0
T4	335221	332488	0	0
T5	272170	267640	0	0
T6	191048	190948	0	0
T7	362836	362783	0	0
T8	34541	34352	0	0
T9	187637	187555	0	0
T10	392846	392749	0	0

RegsTlODValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	612230826	611875301	0	0
T1	390374	390227	0	0
T2	229195	229183	0	0
T3	722867	722715	0	0
T4	335221	332488	0	0
T5	272170	267640	0	0
T6	191048	190948	0	0
T7	362836	362783	0	0
T8	34541	34352	0	0
T9	187637	187555	0	0
T10	392846	392749	0	0

RomTlOAReadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	612230826	611875301	0	0
T1	390374	390227	0	0
T2	229195	229183	0	0
T3	722867	722715	0	0
T4	335221	332488	0	0
T5	272170	267640	0	0
T6	191048	190948	0	0
T7	362836	362783	0	0
T8	34541	34352	0	0
T9	187637	187555	0	0
T10	392846	392749	0	0

RomTlODDataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	612230826	17242599	0	0
T1	390374	12	0	0
T2	229195	160761	0	0
T3	722867	70	0	0
T4	335221	0	0	0
T5	272170	0	0	0
T6	191048	44	0	0
T7	362836	0	0	0
T8	34541	352	0	0
T9	187637	323	0	0
T10	392846	0	0	0
T11	0	199	0	0
T12	0	128601	0	0
T18	0	92	0	0
T19	0	83	0	0

RomTlODDataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	612230826	611875301	0	0
T1	390374	390227	0	0
T2	229195	229183	0	0
T3	722867	722715	0	0
T4	335221	332488	0	0
T5	272170	267640	0	0
T6	191048	190948	0	0
T7	362836	362783	0	0
T8	34541	34352	0	0
T9	187637	187555	0	0
T10	392846	392749	0	0

RomTlODValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	612230826	611875301	0	0
T1	390374	390227	0	0
T2	229195	229183	0	0
T3	722867	722715	0	0
T4	335221	332488	0	0
T5	272170	267640	0	0
T6	191048	190948	0	0
T7	362836	362783	0	0
T8	34541	34352	0	0
T9	187637	187555	0	0
T10	392846	392749	0	0

StabilityChkKmac_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	612230826	539786345	0	0
T1	390374	388195	0	0
T2	229195	98250	0	0
T3	722867	721179	0	0
T4	335221	320837	0	0
T5	272170	256032	0	0
T6	191048	189635	0	0
T7	362836	362654	0	0
T8	34541	32750	0	0
T9	187637	186442	0	0
T10	392846	392368	0	0

StabilityChkkeymgr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	612230826	71836599	0	0
T1	390374	19329	0	0
T2	229195	219344	0	0
T3	722867	1416	0	0
T4	335221	10241	0	0
T5	272170	141	0	0
T6	191048	1290	0	0
T7	362836	106	0	0
T8	34541	1556	0	0
T9	187637	1054	0	0
T10	392846	286	0	0

TlAccessChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	612230826	540036461	0	0
T1	390374	388293	0	0
T2	229195	98382	0	0
T3	722867	721297	0	0
T4	335221	322231	0	0
T5	272170	267484	0	0
T6	191048	189657	0	0
T7	362836	362676	0	0
T8	34541	32794	0	0
T9	187637	186500	0	0
T10	392846	392462	0	0

gen_asserts_with_scrambling.FpvSecCmCheckerFsmAlert_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	612230826	140	0	0
T5	272170	20	0	0
T6	191048	0	0	0
T7	362836	0	0	0
T8	34541	0	0	0
T9	187637	0	0	0
T10	392846	0	0	0
T11	773015	0	0	0
T18	113446	0	0	0
T19	492686	0	0	0
T35	0	10	0	0
T36	0	10	0	0
T37	328204	0	0	0
T38	0	10	0	0
T39	0	10	0	0
T40	0	20	0	0
T41	0	20	0	0
T42	0	10	0	0
T43	0	20	0	0
T44	0	10	0	0

gen_asserts_with_scrambling.FpvSecCmCompareAddrCtrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	612230826	0	0	0

gen_asserts_with_scrambling.FpvSecCmCompareFsmAlert_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	612230826	1078	0	0
T4	335221	5	0	0
T5	272170	20	0	0
T6	191048	0	0	0
T7	362836	0	0	0
T8	34541	0	0	0
T9	187637	0	0	0
T10	392846	0	0	0
T18	113446	0	0	0
T19	492686	0	0	0
T30	0	15	0	0
T31	0	10	0	0
T33	0	10	0	0
T34	0	5	0	0
T35	0	10	0	0
T37	328204	0	0	0
T45	0	10	0	0
T46	0	20	0	0
T47	0	5	0	0

gen_fsm_scramble_enabled_asserts.BusLocalEscChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	612230826	0	0	0