Module Definition
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Module : tlul_adapter_sram
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.78 96.92 85.59 92.59 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_tl_adapter_rom 93.78 96.92 85.59 92.59 100.00



Module Instance : tb.dut.u_tl_adapter_rom

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.78 96.92 85.59 92.59 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.26 91.56 84.30 99.07 96.39 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.98 100.00 98.28 97.33 100.00 79.31 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_cmd_intg_check.u_cmd_intg_chk 100.00 100.00 100.00 100.00
u_err 100.00 100.00 100.00 100.00 100.00
u_reqfifo 95.19 100.00 80.77 100.00 100.00
u_rsp_gen 100.00 100.00 100.00
u_rspfifo 94.22 100.00 81.08 90.00 100.00 100.00
u_sram_byte 100.00 100.00
u_sramreqfifo 89.96 100.00 65.38 94.44 100.00
u_tlul_data_integ_enc_data 0.00 0.00
u_tlul_data_integ_enc_instr 0.00 0.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : tlul_adapter_sram
Line No.TotalCoveredPercent
TOTAL656396.92
ALWAYS934375.00
CONT_ASSIGN10211100.00
CONT_ASSIGN10711100.00
CONT_ASSIGN11411100.00
CONT_ASSIGN11911100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN22211100.00
CONT_ASSIGN22311100.00
CONT_ASSIGN22411100.00
ALWAYS2298787.50
ALWAYS24966100.00
CONT_ASSIGN26311100.00
CONT_ASSIGN26711100.00
CONT_ASSIGN28611100.00
CONT_ASSIGN29111100.00
CONT_ASSIGN29711100.00
CONT_ASSIGN30111100.00
CONT_ASSIGN32111100.00
CONT_ASSIGN32211100.00
CONT_ASSIGN32311100.00
CONT_ASSIGN32411100.00
ALWAYS35466100.00
ALWAYS36655100.00
CONT_ASSIGN37711100.00
CONT_ASSIGN37811100.00
CONT_ASSIGN38711100.00
CONT_ASSIGN38811100.00
CONT_ASSIGN39011100.00
CONT_ASSIGN39111100.00
CONT_ASSIGN39811100.00
CONT_ASSIGN40111100.00
CONT_ASSIGN40511100.00
CONT_ASSIGN40611100.00
CONT_ASSIGN40811100.00
CONT_ASSIGN41511100.00
ALWAYS42133100.00
CONT_ASSIGN44211100.00
CONT_ASSIGN44711100.00
CONT_ASSIGN45200
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
93 1 1
94 1 1
95 1 1
96 0 1
MISSING_ELSE
102 1 1
107 1 1
114 1 1
119 1 1
139 1 1
151 1 1
222 1 1
223 1 1
224 1 1
229 1 1
231 1 1
232 1 1
234 1 1
235 1 1
236 1 1
239 0 1
242 1 1
249 1 1
251 1 1
252 1 1
253 1 1
255 1 1
258 1 1
263 1 1
267 1 1
286 1 1
291 1 1
297 1 1
301 1 1
321 1 1
322 1 1
323 1 1
324 1 1
354 1 1
355 1 1
357 1 1
358 1 1
359 1 1
360 1 1
MISSING_ELSE
366 1 1
367 1 1
369 1 1
370 1 1
371 1 1
MISSING_ELSE
377 1 1
378 1 1
387 1 1
388 1 1
390 1 1
391 1 1
398 1 1
401 1 1
405 1 1
406 1 1
408 1 1
415 1 1
421 1 1
425 1 1
427 1 1
MISSING_ELSE
442 1 1
447 1 1
452 unreachable


Cond Coverage for Module : tlul_adapter_sram
TotalCoveredPercent
Conditions11810185.59
Logical11810185.59
Non-Logical00
Event00

 LINE       95
 EXPRESSION (intg_error || rsp_fifo_error)
             -----1----    -------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10Not Covered

 LINE       102
 EXPRESSION (intg_error | rsp_fifo_error | intg_error_q)
             -----1----   -------2------   ------3-----
-1--2--3-StatusTests
000CoveredT1,T2,T3
001Not Covered
010Not Covered
100Not Covered

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData)) ? ((ByteAccess == 1'b0) ? ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2)) : 1'b0) : 1'b0)
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       107
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------    ----------------2----------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T3,T4
10CoveredT2,T3,T4

 LINE       107
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       107
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       107
 SUB-EXPRESSION ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2))
                 ---------1---------    ----------2----------
-1--2-StatusTests
00CoveredT2,T9,T11
01CoveredT2,T3,T4
10CoveredT2,T3,T4

 LINE       107
 SUB-EXPRESSION (tl_i.a_mask != '1)
                ---------1---------
-1-StatusTests
0CoveredT2,T3,T4
1CoveredT2,T3,T4

 LINE       107
 SUB-EXPRESSION (tl_i.a_size != 2'h2)
                ----------1----------
-1-StatusTests
0CoveredT2,T3,T4
1CoveredT2,T3,T4

 LINE       119
 EXPRESSION (tl_i.a_opcode != Get)
            -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       139
 EXPRESSION (wr_attr_error | wr_vld_error | rd_vld_error | instr_error | tlul_error | intg_error)
             ------1------   ------2-----   ------3-----   -----4-----   -----5----   -----6----
-1--2--3--4--5--6-StatusTests
000000CoveredT1,T2,T3
000001Not Covered
000010CoveredT2,T3,T4
000100Not Covered
001000Unreachable
010000CoveredT2,T12,T13
100000Not Covered

 LINE       222
 EXPRESSION (tl_i_int.a_valid & tl_o_int.a_ready)
             --------1-------   --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T8
11CoveredT1,T2,T3

 LINE       223
 EXPRESSION (tl_o_int.d_valid & tl_i_int.d_ready)
             --------1-------   --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T3,T8
11CoveredT1,T2,T3

 LINE       224
 EXPRESSION (req_o & gnt_i)
             --1--   --2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T8
11CoveredT1,T2,T3

 LINE       235
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

 LINE       252
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------
-1-StatusTests
0CoveredT2,T12,T13
1CoveredT1,T2,T3

 LINE       253
 EXPRESSION (rspfifo_rdata.error | reqfifo_rdata.error)
             ---------1---------   ---------2---------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T12,T13
10Not Covered

 LINE       263
 EXPRESSION (d_valid & reqfifo_rvalid & rspfifo_rvalid & (reqfifo_rdata.op == OpRead))
             ---1---   -------2------   -------3------   --------------4-------------
-1--2--3--4-StatusTests
0111Not Covered
1011Not Covered
1101CoveredT2,T12,T13
1110CoveredT14,T15,T16
1111CoveredT1,T2,T3

 LINE       263
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       291
 EXPRESSION ((vld_rd_rsp & ((~d_error))) ? rspfifo_rdata.data : error_blanking_data)
             -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       291
 SUB-EXPRESSION (vld_rd_rsp & ((~d_error)))
                 -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT17
11CoveredT1,T2,T3

 LINE       297
 EXPRESSION ((vld_rd_rsp && reqfifo_rdata.error) ? error_blanking_integ : (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc))
             -----------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT17

 LINE       297
 SUB-EXPRESSION (vld_rd_rsp && reqfifo_rdata.error)
                 -----1----    ---------2---------
-1--2-StatusTests
01CoveredT2,T12,T13
10CoveredT1,T2,T3
11CoveredT17

 LINE       297
 SUB-EXPRESSION (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc)
                 -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       301
 EXPRESSION ((d_valid && (reqfifo_rdata.op != OpRead)) ? AccessAck : AccessAckData)
             --------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T12,T13

 LINE       301
 SUB-EXPRESSION (d_valid && (reqfifo_rdata.op != OpRead))
                 ---1---    --------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT2,T12,T13

 LINE       301
 SUB-EXPRESSION (reqfifo_rdata.op != OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       301
 EXPRESSION (d_valid ? reqfifo_rdata.size : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       301
 EXPRESSION (d_valid ? reqfifo_rdata.source : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       301
 EXPRESSION (d_valid && d_error)
             ---1---    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT2,T12,T13

 LINE       301
 EXPRESSION ((gnt_i | error_internal) & reqfifo_wready & sramreqfifo_wready)
             ------------1-----------   -------2------   ---------3--------
-1--2--3-StatusTests
011CoveredT2,T3,T8
101CoveredT8,T11,T12
110Not Covered
111CoveredT1,T2,T3

 LINE       301
 SUB-EXPRESSION (gnt_i | error_internal)
                 --1--   -------2------
-1--2-StatusTests
00CoveredT2,T3,T8
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       321
 EXPRESSION (tl_i_int.a_valid & reqfifo_wready & ((~error_internal)))
             --------1-------   -------2------   ---------3---------
-1--2--3-StatusTests
011Not Covered
101CoveredT8,T11,T12
110CoveredT2,T12,T13
111CoveredT1,T2,T3

 LINE       323
 EXPRESSION (tl_i_int.a_valid & (tl_i_int.a_opcode inside {PutFullData, PutPartialData}))
             --------1-------   ----------------------------2---------------------------
-1--2-StatusTests
01CoveredT3,T4,T5
10CoveredT1,T2,T3
11CoveredT2,T12,T13

 LINE       324
 EXPRESSION (tl_i_int.a_valid ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       360
 EXPRESSION ((tl_i_int.a_mask[i] && we_o) ? tl_i_int.a_data[(8 * i)+:8] : '0)
             --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T12,T13

 LINE       360
 SUB-EXPRESSION (tl_i_int.a_mask[i] && we_o)
                 ---------1--------    --2-
-1--2-StatusTests
01CoveredT2,T12,T13
10CoveredT1,T2,T3
11CoveredT2,T12,T13

 LINE       391
 EXPRESSION ((tl_i_int.a_opcode != Get) ? OpWrite : OpRead)
             -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       391
 SUB-EXPRESSION (tl_i_int.a_opcode != Get)
                -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       405
 EXPRESSION (sram_ack & ((~we_o)))
             ----1---   ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       408
 EXPRESSION (rvalid_i & reqfifo_rvalid)
             ----1---   -------2------
-1--2-StatusTests
01CoveredT1,T2,T8
10Not Covered
11CoveredT1,T2,T3

 LINE       447
 EXPRESSION (((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error))) ? reqfifo_rready : 1'b0)
             ----------------------------1----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       447
 SUB-EXPRESSION ((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error)))
                 --------------1-------------   ------------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T12,T13
11CoveredT1,T2,T3

 LINE       447
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Module : tlul_adapter_sram
Line No.TotalCoveredPercent
Branches 27 25 92.59
TERNARY 107 2 2 100.00
TERNARY 291 2 2 100.00
TERNARY 297 3 3 100.00
TERNARY 324 2 2 100.00
TERNARY 447 2 2 100.00
IF 93 3 2 66.67
IF 231 4 3 75.00
IF 251 3 3 100.00
IF 357 2 2 100.00
IF 369 2 2 100.00
IF 425 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 107 (((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))) ?

Branches:
-1-StatusTests
1 Covered T2,T3,T4
0 Covered T1,T2,T3


LineNo. Expression -1-: 291 ((vld_rd_rsp & (~d_error))) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 297 ((vld_rd_rsp && reqfifo_rdata.error)) ? -2-: 297 (vld_rd_rsp) ?

Branches:
-1--2-StatusTests
1 - Covered T17
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 324 (tl_i_int.a_valid) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 447 (((reqfifo_rdata.op == OpRead) & (~reqfifo_rdata.error))) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 93 if ((!rst_ni)) -2-: 95 if ((intg_error || rsp_fifo_error))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Not Covered
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 231 if (reqfifo_rvalid) -2-: 232 if (reqfifo_rdata.error) -3-: 235 if ((reqfifo_rdata.op == OpRead))

Branches:
-1--2--3-StatusTests
1 1 - Covered T2,T12,T13
1 0 1 Covered T1,T2,T3
1 0 0 Not Covered
0 - - Covered T1,T2,T3


LineNo. Expression -1-: 251 if (reqfifo_rvalid) -2-: 252 if ((reqfifo_rdata.op == OpRead))

Branches:
-1--2-StatusTests
1 1 Covered T1,T2,T3
1 0 Covered T2,T12,T13
0 - Covered T1,T2,T3


LineNo. Expression -1-: 357 if (tl_i_int.a_valid)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 369 if (tl_i_int.a_valid)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 425 if ((|sramreqfifo_rdata.mask))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Module : tlul_adapter_sram
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 14 14 100.00 14 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 14 14 100.00 14 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AddrOutKnown_A 612230826 611875301 0 0
DataIntgOptions_A 628 628 0 0
ReqOutKnown_A 612230826 611875301 0 0
SramDwHasByteGranularity_A 628 628 0 0
SramDwIsMultipleOfTlulWidth_A 628 628 0 0
TlOutKnown_A 612230826 611875301 0 0
TlOutPayloadKnown_A 612230826 17242599 0 0
TlOutPayloadKnown_AKnownEnable 612230826 611875301 0 0
WdataOutKnown_A 612230826 611875301 0 0
WeOutKnown_A 612230826 611875301 0 0
WmaskOutKnown_A 612230826 611875301 0 0
adapterNoReadOrWrite 628 628 0 0
rvalidHighReqFifoEmpty 612230826 64661 0 0
rvalidHighWhenRspFifoFull 612230826 64661 0 0


AddrOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 612230826 611875301 0 0
T1 390374 390227 0 0
T2 229195 229183 0 0
T3 722867 722715 0 0
T4 335221 332488 0 0
T5 272170 267640 0 0
T6 191048 190948 0 0
T7 362836 362783 0 0
T8 34541 34352 0 0
T9 187637 187555 0 0
T10 392846 392749 0 0

DataIntgOptions_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 628 628 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

ReqOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 612230826 611875301 0 0
T1 390374 390227 0 0
T2 229195 229183 0 0
T3 722867 722715 0 0
T4 335221 332488 0 0
T5 272170 267640 0 0
T6 191048 190948 0 0
T7 362836 362783 0 0
T8 34541 34352 0 0
T9 187637 187555 0 0
T10 392846 392749 0 0

SramDwHasByteGranularity_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 628 628 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

SramDwIsMultipleOfTlulWidth_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 628 628 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

TlOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 612230826 611875301 0 0
T1 390374 390227 0 0
T2 229195 229183 0 0
T3 722867 722715 0 0
T4 335221 332488 0 0
T5 272170 267640 0 0
T6 191048 190948 0 0
T7 362836 362783 0 0
T8 34541 34352 0 0
T9 187637 187555 0 0
T10 392846 392749 0 0

TlOutPayloadKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 612230826 17242599 0 0
T1 390374 12 0 0
T2 229195 160761 0 0
T3 722867 70 0 0
T4 335221 0 0 0
T5 272170 0 0 0
T6 191048 44 0 0
T7 362836 0 0 0
T8 34541 352 0 0
T9 187637 323 0 0
T10 392846 0 0 0
T11 0 199 0 0
T12 0 128601 0 0
T18 0 92 0 0
T19 0 83 0 0

TlOutPayloadKnown_AKnownEnable
NameAttemptsReal SuccessesFailuresIncomplete
Total 612230826 611875301 0 0
T1 390374 390227 0 0
T2 229195 229183 0 0
T3 722867 722715 0 0
T4 335221 332488 0 0
T5 272170 267640 0 0
T6 191048 190948 0 0
T7 362836 362783 0 0
T8 34541 34352 0 0
T9 187637 187555 0 0
T10 392846 392749 0 0

WdataOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 612230826 611875301 0 0
T1 390374 390227 0 0
T2 229195 229183 0 0
T3 722867 722715 0 0
T4 335221 332488 0 0
T5 272170 267640 0 0
T6 191048 190948 0 0
T7 362836 362783 0 0
T8 34541 34352 0 0
T9 187637 187555 0 0
T10 392846 392749 0 0

WeOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 612230826 611875301 0 0
T1 390374 390227 0 0
T2 229195 229183 0 0
T3 722867 722715 0 0
T4 335221 332488 0 0
T5 272170 267640 0 0
T6 191048 190948 0 0
T7 362836 362783 0 0
T8 34541 34352 0 0
T9 187637 187555 0 0
T10 392846 392749 0 0

WmaskOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 612230826 611875301 0 0
T1 390374 390227 0 0
T2 229195 229183 0 0
T3 722867 722715 0 0
T4 335221 332488 0 0
T5 272170 267640 0 0
T6 191048 190948 0 0
T7 362836 362783 0 0
T8 34541 34352 0 0
T9 187637 187555 0 0
T10 392846 392749 0 0

adapterNoReadOrWrite
NameAttemptsReal SuccessesFailuresIncomplete
Total 628 628 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

rvalidHighReqFifoEmpty
NameAttemptsReal SuccessesFailuresIncomplete
Total 612230826 64661 0 0
T1 390374 3 0 0
T2 229195 937 0 0
T3 722867 70 0 0
T4 335221 0 0 0
T5 272170 0 0 0
T6 191048 44 0 0
T7 362836 0 0 0
T8 34541 69 0 0
T9 187637 323 0 0
T10 392846 0 0 0
T11 0 77 0 0
T12 0 1051 0 0
T18 0 92 0 0
T19 0 83 0 0

rvalidHighWhenRspFifoFull
NameAttemptsReal SuccessesFailuresIncomplete
Total 612230826 64661 0 0
T1 390374 3 0 0
T2 229195 937 0 0
T3 722867 70 0 0
T4 335221 0 0 0
T5 272170 0 0 0
T6 191048 44 0 0
T7 362836 0 0 0
T8 34541 69 0 0
T9 187637 323 0 0
T10 392846 0 0 0
T11 0 77 0 0
T12 0 1051 0 0
T18 0 92 0 0
T19 0 83 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%