Unified Coverage Report :: Module :: rom_ctrl

Module : rom_ctrl

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.98	100.00	98.28	97.33		100.00	79.31

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	94.98	100.00	98.28	97.33		100.00	79.31

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.98	100.00	98.28	97.33		100.00	79.31

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.45	96.96	93.11	97.88	100.00	98.68	98.04

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_alert_tx[0].u_alert_sender	100.00			100.00
gen_fsm_scramble_enabled.u_checker_fsm	96.36	100.00	97.22	90.00	100.00	100.00	90.91
gen_rom_scramble_enabled.u_rom	97.06	88.24		100.00		100.00	100.00
regs_tlul_assert_device	100.00	100.00				100.00	100.00
rom_ctrl_regs_csr_assert	100.00						100.00
rom_tlul_assert_device	99.30	100.00				100.00	97.90
u_mux	95.24	100.00	85.71			100.00
u_reg_regs	99.72	99.41	99.21	100.00		100.00	100.00
u_tl_adapter_rom	94.13	91.45	84.93	99.07		95.18	100.00
u_tl_rom_h2d_buf	100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rom_ctrl

	Line No.	Total	Covered	Percent
TOTAL		65	65	100.00
CONT_ASSIGN	120	1	1	100.00
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	127	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	207	1	1	100.00
CONT_ASSIGN	253	1	1	100.00
CONT_ASSIGN	308	1	1	100.00
CONT_ASSIGN	409	1	1	100.00
CONT_ASSIGN	409	1	1	100.00
CONT_ASSIGN	409	1	1	100.00
CONT_ASSIGN	409	1	1	100.00
CONT_ASSIGN	409	1	1	100.00
CONT_ASSIGN	409	1	1	100.00
CONT_ASSIGN	409	1	1	100.00
CONT_ASSIGN	409	1	1	100.00
CONT_ASSIGN	410	1	1	100.00
CONT_ASSIGN	410	1	1	100.00
CONT_ASSIGN	410	1	1	100.00
CONT_ASSIGN	410	1	1	100.00
CONT_ASSIGN	410	1	1	100.00
CONT_ASSIGN	410	1	1	100.00
CONT_ASSIGN	410	1	1	100.00
CONT_ASSIGN	410	1	1	100.00
CONT_ASSIGN	412	1	1	100.00
CONT_ASSIGN	412	1	1	100.00
CONT_ASSIGN	412	1	1	100.00
CONT_ASSIGN	412	1	1	100.00
CONT_ASSIGN	412	1	1	100.00
CONT_ASSIGN	412	1	1	100.00
CONT_ASSIGN	412	1	1	100.00
CONT_ASSIGN	412	1	1	100.00
CONT_ASSIGN	413	1	1	100.00
CONT_ASSIGN	413	1	1	100.00
CONT_ASSIGN	413	1	1	100.00
CONT_ASSIGN	413	1	1	100.00
CONT_ASSIGN	413	1	1	100.00
CONT_ASSIGN	413	1	1	100.00
CONT_ASSIGN	413	1	1	100.00
CONT_ASSIGN	413	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	422	1	1	100.00
CONT_ASSIGN	425	1	1	100.00
CONT_ASSIGN	426	1	1	100.00
CONT_ASSIGN	427	1	1	100.00
CONT_ASSIGN	428	1	1	100.00
CONT_ASSIGN	433	1	1	100.00
CONT_ASSIGN	437	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv' or '../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
120	1	1
125	1	1
126	1	1
127	1	1
128	1	1
131	1	1
207	1	1
253	1	1
308	1	1
409	8	8
410	8	8
412	8	8
413	8	8
415	8	8
416	8	8
420	1	1
422	1	1
425	1	1
426	1	1
427	1	1
428	1	1
433	1	1
437	1	1

---

Cond Coverage for Module : rom_ctrl

	Total	Covered	Percent
Conditions	58	57	98.28
Logical	58	57	98.28
Non-Logical	0	0
Event	0	0

 LINE       207
 EXPRESSION (rom_tl_i.a_valid ? rom_tl_i.a_address[2+:RomIndexWidth] : '0)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       253
 EXPRESSION (bus_rom_rvalid_raw & ((!internal_alert)))
             ---------1--------   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T15
1	1	Covered	T2,T3,T4

 LINE       413
 EXPRESSION (exp_digest_de && (0 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       413
 SUB-EXPRESSION (0 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       413
 EXPRESSION (exp_digest_de && (1 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       413
 SUB-EXPRESSION (1 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       413
 EXPRESSION (exp_digest_de && (2 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       413
 SUB-EXPRESSION (2 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       413
 EXPRESSION (exp_digest_de && (3 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       413
 SUB-EXPRESSION (3 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       413
 EXPRESSION (exp_digest_de && (4 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       413
 SUB-EXPRESSION (4 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       413
 EXPRESSION (exp_digest_de && (5 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       413
 SUB-EXPRESSION (5 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       413
 EXPRESSION (exp_digest_de && (6 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       413
 SUB-EXPRESSION (6 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       413
 EXPRESSION (exp_digest_de && (7 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       413
 SUB-EXPRESSION (7 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION (rom_integrity_error | reg_integrity_error)
             ---------1---------   ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T34,T35,T36
1	0	Not Covered

 LINE       422
 EXPRESSION (checker_alert | mux_alert)
             ------1------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T5,T15
1	0	Covered	T1,T2,T5

 LINE       433
 EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
             ---------1---------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T24
1	0	Covered	T1,T2,T3
1	1	Covered	T6,T7,T24

 LINE       437
 EXPRESSION (bus_integrity_error | checker_alert | mux_alert)
             ---------1---------   ------2------   ----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T2,T5,T15
0	1	0	Covered	T1,T2,T5
1	0	0	Covered	T34,T35,T36

---

Toggle Coverage for Module : rom_ctrl

	Total	Covered	Percent
Totals	61	56	91.80
Total Bits	2882	2805	97.33
Total Bits 0->1	1441	1402	97.29
Total Bits 1->0	1441	1403	97.36

Ports	61	56	91.80
Port Bits	2882	2805	97.33
Port Bits 0->1	1441	1402	97.29
Port Bits 1->0	1441	1403	97.36

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rom_cfg_i.cfg[3:0]	No	No		No		INPUT
rom_cfg_i.cfg_en	No	No		No		INPUT
rom_tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rom_tl_i.a_user.data_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
rom_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
rom_tl_i.a_user.instr_type[3:0]	Yes	Yes	T2,T4,T9	Yes	T2,T4,T9	INPUT
rom_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
rom_tl_i.a_data[31:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
rom_tl_i.a_mask[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
rom_tl_i.a_address[31:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
rom_tl_i.a_source[7:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
rom_tl_i.a_size[1:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
rom_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
rom_tl_i.a_opcode[2:0]	Yes	Yes	T2,T4,T9	Yes	T2,T4,T9	INPUT
rom_tl_i.a_valid	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
rom_tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
rom_tl_o.d_error	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
rom_tl_o.d_user.data_intg[6:0]	Yes	Yes	T3,T4,T9	Yes	T3,T4,T9	OUTPUT
rom_tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T2,*T3,*T4	Yes	T2,T3,T4	OUTPUT
rom_tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
rom_tl_o.d_data[31:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
rom_tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
rom_tl_o.d_source[7:0]	Yes	Yes	T3,T4,T9	Yes	T3,T4,T9	OUTPUT
rom_tl_o.d_size[1:0]	Yes	Yes	T3,T4,T9	Yes	T3,T4,T9	OUTPUT
rom_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
rom_tl_o.d_opcode[0]	Yes	Yes	*T20,*T21,*T22	Yes	T20,T21,T22	OUTPUT
rom_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
rom_tl_o.d_valid	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
regs_tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_user.data_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
regs_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
regs_tl_i.a_user.instr_type[3:0]	Yes	Yes	T5,T15,T30	Yes	T5,T15,T37	INPUT
regs_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_data[31:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
regs_tl_i.a_mask[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
regs_tl_i.a_address[31:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
regs_tl_i.a_source[7:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
regs_tl_i.a_size[1:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
regs_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_opcode[2:0]	Yes	Yes	T5,T7,T14	Yes	T5,T7,T15	INPUT
regs_tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
regs_tl_o.d_error	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
regs_tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
regs_tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T2,*T3,*T4	Yes	T2,T3,T4	OUTPUT
regs_tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
regs_tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
regs_tl_o.d_size[1:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
regs_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
regs_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T1,T2,T5	Yes	T1,T2,T5	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T1,T2,T5	Yes	T1,T2,T5	OUTPUT
pwrmgr_data_o.good[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
pwrmgr_data_o.done[3:0]	Yes	Yes	T1,T2,T3	Yes	T2,T3,T4	OUTPUT
keymgr_data_o.valid	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	OUTPUT
keymgr_data_o.data[255:0]	Yes	Yes	T2,T3,T5	Yes	T2,T3,T4	OUTPUT
kmac_data_i.error	No	Yes	T1,T8,T29	No		INPUT
kmac_data_i.digest_share1[383:0]	Yes	Yes	T1,T2,T5	Yes	T2,T5,T8	INPUT
kmac_data_i.digest_share0[383:0]	Yes	Yes	T1,T2,T4	Yes	T2,T3,T5	INPUT
kmac_data_i.done	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
kmac_data_i.ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
kmac_data_o.last	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
kmac_data_o.strb[7:0]	No	No		No		OUTPUT
kmac_data_o.data[38:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
kmac_data_o.data[63:39]	No	No		No		OUTPUT
kmac_data_o.valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Module : rom_ctrl

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
TERNARY	207	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv' or '../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	207	(rom_tl_i.a_valid) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Module : rom_ctrl

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	29	29	100.00	23	79.31
Cover properties	0	0		0
Cover sequences	0	0		0
Total	29	29	100.00	23	79.31

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxOKnown_A	561396974	561057131	0	0
BusRomIndicesMatch_A	561369254	561041072	0	0
FpvSecCmFifoRptrCheck_A	561396974	0	0	0
FpvSecCmFifoWptrCheck_A	561396974	0	0	0
FpvSecCmRegWeOnehotCheck_A	561396974	140	0	0
KeymgrDataODataKnown_A	561396974	70601399	0	0
KeymgrDataODataKnown_AKnownEnable	561396974	561057131	0	0
KeymgrDataOValidKnown_A	561396974	561057131	0	0
KeymgrValidChk_A	561396974	0	0	627
KmacDataODataKnown_A	561396974	490205287	0	0
KmacDataODataKnown_AKnownEnable	561396974	561057131	0	0
KmacDataOValidKnown_A	561396974	561057131	0	0
PwrmgrDataChk_A	561396974	0	0	627
PwrmgrDataOKnown_A	561396974	561057131	0	0
RegsTlOAReadyKnown_A	561396974	561057131	0	0
RegsTlODDataKnown_A	561396974	7942087	0	0
RegsTlODDataKnown_AKnownEnable	561396974	561057131	0	0
RegsTlODValidKnown_A	561396974	561057131	0	0
RomTlOAReadyKnown_A	561396974	561057131	0	0
RomTlODDataKnown_A	561396974	11818538	0	0
RomTlODDataKnown_AKnownEnable	561396974	561057131	0	0
RomTlODValidKnown_A	561396974	561057131	0	0
StabilityChkKmac_A	561396974	490200664	0	0
StabilityChkkeymgr_A	561396974	70599197	0	0
TlAccessChk_A	561396974	490455732	0	0
gen_asserts_with_scrambling.FpvSecCmCheckerFsmAlert_A	561396974	140	0	0
gen_asserts_with_scrambling.FpvSecCmCompareAddrCtrCheck_A	561396974	0	0	0
gen_asserts_with_scrambling.FpvSecCmCompareFsmAlert_A	561396974	964	0	0
gen_fsm_scramble_enabled_asserts.BusLocalEscChk_A	561396974	0	0	0

AlertTxOKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	561396974	561057131	0	0
T1	65862	65697	0	0
T2	400170	399839	0	0
T3	526803	526620	0	0
T4	853562	853397	0	0
T5	724565	724328	0	0
T6	81441	81383	0	0
T7	318871	318806	0	0
T8	32978	32861	0	0
T9	247527	247439	0	0
T10	99446	99274	0	0

BusRomIndicesMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	561369254	561041072	0	0
T1	65862	65697	0	0
T2	400160	399837	0	0
T3	526803	526620	0	0
T4	853562	853397	0	0
T5	724565	724328	0	0
T6	81441	81383	0	0
T7	318871	318806	0	0
T8	32978	32861	0	0
T9	247527	247439	0	0
T10	99446	99274	0	0

FpvSecCmFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	561396974	0	0	0

FpvSecCmFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	561396974	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	561396974	140	0	0
T34	24909	10	0	0
T35	0	20	0	0
T36	0	10	0	0
T38	0	20	0	0
T39	0	20	0	0
T40	0	10	0	0
T41	0	10	0	0
T42	0	10	0	0
T43	0	20	0	0
T44	0	10	0	0
T45	361601	0	0	0
T46	105179	0	0	0
T47	132446	0	0	0
T48	525212	0	0	0
T49	34458	0	0	0
T50	208273	0	0	0
T51	49558	0	0	0
T52	17160	0	0	0
T53	704513	0	0	0

KeymgrDataODataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	561396974	70601399	0	0
T1	65862	4	0	0
T2	400170	21539	0	0
T3	526803	1789	0	0
T4	853562	968	0	0
T5	724565	15049	0	0
T6	81441	139	0	0
T7	318871	287	0	0
T8	32978	53	0	0
T9	247527	1265	0	0
T10	99446	1310	0	0

KeymgrDataODataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	561396974	561057131	0	0
T1	65862	65697	0	0
T2	400170	399839	0	0
T3	526803	526620	0	0
T4	853562	853397	0	0
T5	724565	724328	0	0
T6	81441	81383	0	0
T7	318871	318806	0	0
T8	32978	32861	0	0
T9	247527	247439	0	0
T10	99446	99274	0	0

KeymgrDataOValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	561396974	561057131	0	0
T1	65862	65697	0	0
T2	400170	399839	0	0
T3	526803	526620	0	0
T4	853562	853397	0	0
T5	724565	724328	0	0
T6	81441	81383	0	0
T7	318871	318806	0	0
T8	32978	32861	0	0
T9	247527	247439	0	0
T10	99446	99274	0	0

KeymgrValidChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	561396974	0	0	627

KmacDataODataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	561396974	490205287	0	0
T1	65862	65504	0	0
T2	400170	397205	0	0
T3	526803	524686	0	0
T4	853562	852359	0	0
T5	724565	722622	0	0
T6	81441	81199	0	0
T7	318871	318438	0	0
T8	32978	32752	0	0
T9	247527	246118	0	0
T10	99446	97854	0	0

KmacDataODataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	561396974	561057131	0	0
T1	65862	65697	0	0
T2	400170	399839	0	0
T3	526803	526620	0	0
T4	853562	853397	0	0
T5	724565	724328	0	0
T6	81441	81383	0	0
T7	318871	318806	0	0
T8	32978	32861	0	0
T9	247527	247439	0	0
T10	99446	99274	0	0

KmacDataOValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	561396974	561057131	0	0
T1	65862	65697	0	0
T2	400170	399839	0	0
T3	526803	526620	0	0
T4	853562	853397	0	0
T5	724565	724328	0	0
T6	81441	81383	0	0
T7	318871	318806	0	0
T8	32978	32861	0	0
T9	247527	247439	0	0
T10	99446	99274	0	0

PwrmgrDataChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	561396974	0	0	627

PwrmgrDataOKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	561396974	561057131	0	0
T1	65862	65697	0	0
T2	400170	399839	0	0
T3	526803	526620	0	0
T4	853562	853397	0	0
T5	724565	724328	0	0
T6	81441	81383	0	0
T7	318871	318806	0	0
T8	32978	32861	0	0
T9	247527	247439	0	0
T10	99446	99274	0	0

RegsTlOAReadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	561396974	561057131	0	0
T1	65862	65697	0	0
T2	400170	399839	0	0
T3	526803	526620	0	0
T4	853562	853397	0	0
T5	724565	724328	0	0
T6	81441	81383	0	0
T7	318871	318806	0	0
T8	32978	32861	0	0
T9	247527	247439	0	0
T10	99446	99274	0	0

RegsTlODDataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	561396974	7942087	0	0
T1	65862	1	0	0
T2	400170	35	0	0
T3	526803	32	0	0
T4	853562	32	0	0
T5	724565	29	0	0
T6	81441	2	0	0
T7	318871	9	0	0
T8	32978	8	0	0
T9	247527	0	0	0
T10	99446	32	0	0
T15	0	19	0	0

RegsTlODDataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	561396974	561057131	0	0
T1	65862	65697	0	0
T2	400170	399839	0	0
T3	526803	526620	0	0
T4	853562	853397	0	0
T5	724565	724328	0	0
T6	81441	81383	0	0
T7	318871	318806	0	0
T8	32978	32861	0	0
T9	247527	247439	0	0
T10	99446	99274	0	0

RegsTlODValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	561396974	561057131	0	0
T1	65862	65697	0	0
T2	400170	399839	0	0
T3	526803	526620	0	0
T4	853562	853397	0	0
T5	724565	724328	0	0
T6	81441	81383	0	0
T7	318871	318806	0	0
T8	32978	32861	0	0
T9	247527	247439	0	0
T10	99446	99274	0	0

RomTlOAReadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	561396974	561057131	0	0
T1	65862	65697	0	0
T2	400170	399839	0	0
T3	526803	526620	0	0
T4	853562	853397	0	0
T5	724565	724328	0	0
T6	81441	81383	0	0
T7	318871	318806	0	0
T8	32978	32861	0	0
T9	247527	247439	0	0
T10	99446	99274	0	0

RomTlODDataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	561396974	11818538	0	0
T2	400170	3	0	0
T3	526803	409	0	0
T4	853562	68	0	0
T5	724565	0	0	0
T6	81441	0	0	0
T7	318871	0	0	0
T8	32978	0	0	0
T9	247527	344	0	0
T10	99446	70	0	0
T14	198344	202	0	0
T15	0	3	0	0
T16	0	128	0	0
T17	0	88	0	0
T18	0	273	0	0

RomTlODDataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	561396974	561057131	0	0
T1	65862	65697	0	0
T2	400170	399839	0	0
T3	526803	526620	0	0
T4	853562	853397	0	0
T5	724565	724328	0	0
T6	81441	81383	0	0
T7	318871	318806	0	0
T8	32978	32861	0	0
T9	247527	247439	0	0
T10	99446	99274	0	0

RomTlODValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	561396974	561057131	0	0
T1	65862	65697	0	0
T2	400170	399839	0	0
T3	526803	526620	0	0
T4	853562	853397	0	0
T5	724565	724328	0	0
T6	81441	81383	0	0
T7	318871	318806	0	0
T8	32978	32861	0	0
T9	247527	247439	0	0
T10	99446	99274	0	0

StabilityChkKmac_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	561396974	490200664	0	0
T1	65862	65502	0	0
T2	400170	397201	0	0
T3	526803	524684	0	0
T4	853562	852357	0	0
T5	724565	722619	0	0
T6	81441	81198	0	0
T7	318871	318437	0	0
T8	32978	32750	0	0
T9	247527	246117	0	0
T10	99446	97852	0	0

StabilityChkkeymgr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	561396974	70599197	0	0
T1	65862	3	0	0
T2	400170	21525	0	0
T3	526803	1787	0	0
T4	853562	966	0	0
T5	724565	15035	0	0
T6	81441	138	0	0
T7	318871	286	0	0
T8	32978	52	0	0
T9	247527	1264	0	0
T10	99446	1308	0	0

TlAccessChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	561396974	490455732	0	0
T1	65862	65693	0	0
T2	400170	397685	0	0
T3	526803	524831	0	0
T4	853562	852429	0	0
T5	724565	722823	0	0
T6	81441	81244	0	0
T7	318871	318519	0	0
T8	32978	32808	0	0
T9	247527	246174	0	0
T10	99446	97964	0	0

gen_asserts_with_scrambling.FpvSecCmCheckerFsmAlert_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	561396974	140	0	0
T34	24909	10	0	0
T35	0	20	0	0
T36	0	10	0	0
T38	0	20	0	0
T39	0	20	0	0
T40	0	10	0	0
T41	0	10	0	0
T42	0	10	0	0
T43	0	20	0	0
T44	0	10	0	0
T45	361601	0	0	0
T46	105179	0	0	0
T47	132446	0	0	0
T48	525212	0	0	0
T49	34458	0	0	0
T50	208273	0	0	0
T51	49558	0	0	0
T52	17160	0	0	0
T53	704513	0	0	0

gen_asserts_with_scrambling.FpvSecCmCompareAddrCtrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	561396974	0	0	0

gen_asserts_with_scrambling.FpvSecCmCompareFsmAlert_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	561396974	964	0	0
T2	400170	15	0	0
T3	526803	0	0	0
T4	853562	0	0	0
T5	724565	10	0	0
T6	81441	0	0	0
T7	318871	0	0	0
T8	32978	0	0	0
T9	247527	0	0	0
T10	99446	0	0	0
T13	0	10	0	0
T14	198344	0	0	0
T31	0	5	0	0
T32	0	15	0	0
T33	0	20	0	0
T54	0	5	0	0
T55	0	5	0	0
T56	0	5	0	0
T57	0	20	0	0

gen_fsm_scramble_enabled_asserts.BusLocalEscChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	561396974	0	0	0