Unified Coverage Report :: Module :: rom_ctrl_regs_reg_top

Module : rom_ctrl_regs_reg_top

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl_regs_reg_top.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg_regs	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg_regs

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.72	99.41	99.21	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.98	100.00	98.28	97.33		100.00	79.31	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_alert_test	100.00	100.00
u_chk	100.00	100.00		100.00			100.00
u_digest_0	100.00	100.00	100.00			100.00
u_digest_1	100.00	100.00	100.00			100.00
u_digest_2	100.00	100.00	100.00			100.00
u_digest_3	100.00	100.00	100.00			100.00
u_digest_4	100.00	100.00	100.00			100.00
u_digest_5	100.00	100.00	100.00			100.00
u_digest_6	100.00	100.00	100.00			100.00
u_digest_7	100.00	100.00	100.00			100.00
u_exp_digest_0	100.00	100.00	100.00			100.00
u_exp_digest_1	100.00	100.00	100.00			100.00
u_exp_digest_2	100.00	100.00	100.00			100.00
u_exp_digest_3	100.00	100.00	100.00			100.00
u_exp_digest_4	100.00	100.00	100.00			100.00
u_exp_digest_5	100.00	100.00	100.00			100.00
u_exp_digest_6	100.00	100.00	100.00			100.00
u_exp_digest_7	100.00	100.00	100.00			100.00
u_fatal_alert_cause_checker_error	100.00	100.00	100.00			100.00
u_fatal_alert_cause_integrity_error	100.00	100.00	100.00			100.00
u_prim_reg_we_check	100.00	100.00		100.00
u_reg_if	98.67	97.14	97.53			100.00	100.00
u_rsp_intg_gen	100.00	100.00					100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rom_ctrl_regs_reg_top

	Line No.	Total	Covered	Percent
TOTAL		76	76	100.00
ALWAYS	68	4	4	100.00
CONT_ASSIGN	77	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	119	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
ALWAYS	689	19	19	100.00
CONT_ASSIGN	710	1	1	100.00
ALWAYS	714	1	1	100.00
CONT_ASSIGN	736	1	1	100.00
CONT_ASSIGN	738	1	1	100.00
ALWAYS	742	19	19	100.00
ALWAYS	765	21	21	100.00
CONT_ASSIGN	851	0	0
CONT_ASSIGN	859	1	1	100.00
CONT_ASSIGN	860	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl_regs_reg_top.sv' or '../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl_regs_reg_top.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
69	1	1
70	1	1
71	1	1
			MISSING_ELSE
77	1	1
89	1	1
90	1	1
118	1	1
119	1	1
149	1	1
163	1	1
689	1	1
690	1	1
691	1	1
692	1	1
693	1	1
694	1	1
695	1	1
696	1	1
697	1	1
698	1	1
699	1	1
700	1	1
701	1	1
702	1	1
703	1	1
704	1	1
705	1	1
706	1	1
707	1	1
710	1	1
714	1	1
736	1	1
738	1	1
742	1	1
743	1	1
744	1	1
745	1	1
746	1	1
747	1	1
748	1	1
749	1	1
750	1	1
751	1	1
752	1	1
753	1	1
754	1	1
755	1	1
756	1	1
757	1	1
758	1	1
759	1	1
760	1	1
765	1	1
766	1	1
768	1	1
772	1	1
773	1	1
777	1	1
781	1	1
785	1	1
789	1	1
793	1	1
797	1	1
801	1	1
805	1	1
809	1	1
813	1	1
817	1	1
821	1	1
825	1	1
829	1	1
833	1	1
837	1	1
851		unreachable
859	1	1
860	1	1

---

Cond Coverage for Module : rom_ctrl_regs_reg_top

	Total	Covered	Percent
Conditions	135	135	100.00
Logical	135	135	100.00
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (reg_we && ((!addrmiss)))
             ---1--    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T20,T21,T22
1	1	Covered	T6,T7,T24

 LINE       70
 EXPRESSION (intg_err || reg_we_err)
             ----1---    -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T34,T35,T36
1	0	Covered	T67,T68,T69

 LINE       77
 EXPRESSION (err_q | intg_err | reg_we_err)
             --1--   ----2---   -----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T34,T35,T36
0	1	0	Covered	T67,T68,T69
1	0	0	Covered	T34,T35,T36

 LINE       119
 EXPRESSION (addrmiss | wr_err | intg_err)
             ----1---   ---2--   ----3---

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T67,T68,T69
0	1	0	Covered	T20,T21,T22
1	0	0	Covered	T20,T21,T22

 LINE       690
 EXPRESSION (reg_addr == rom_ctrl_reg_pkg::ROM_CTRL_ALERT_TEST_OFFSET)
            -----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T6,T7

 LINE       691
 EXPRESSION (reg_addr == rom_ctrl_reg_pkg::ROM_CTRL_FATAL_ALERT_CAUSE_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T5

 LINE       692
 EXPRESSION (reg_addr == rom_ctrl_reg_pkg::ROM_CTRL_DIGEST_0_OFFSET)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       693
 EXPRESSION (reg_addr == rom_ctrl_reg_pkg::ROM_CTRL_DIGEST_1_OFFSET)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T10

 LINE       694
 EXPRESSION (reg_addr == rom_ctrl_reg_pkg::ROM_CTRL_DIGEST_2_OFFSET)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       695
 EXPRESSION (reg_addr == rom_ctrl_reg_pkg::ROM_CTRL_DIGEST_3_OFFSET)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       696
 EXPRESSION (reg_addr == rom_ctrl_reg_pkg::ROM_CTRL_DIGEST_4_OFFSET)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T10

 LINE       697
 EXPRESSION (reg_addr == rom_ctrl_reg_pkg::ROM_CTRL_DIGEST_5_OFFSET)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       698
 EXPRESSION (reg_addr == rom_ctrl_reg_pkg::ROM_CTRL_DIGEST_6_OFFSET)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       699
 EXPRESSION (reg_addr == rom_ctrl_reg_pkg::ROM_CTRL_DIGEST_7_OFFSET)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       700
 EXPRESSION (reg_addr == rom_ctrl_reg_pkg::ROM_CTRL_EXP_DIGEST_0_OFFSET)
            ------------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       701
 EXPRESSION (reg_addr == rom_ctrl_reg_pkg::ROM_CTRL_EXP_DIGEST_1_OFFSET)
            ------------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       702
 EXPRESSION (reg_addr == rom_ctrl_reg_pkg::ROM_CTRL_EXP_DIGEST_2_OFFSET)
            ------------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       703
 EXPRESSION (reg_addr == rom_ctrl_reg_pkg::ROM_CTRL_EXP_DIGEST_3_OFFSET)
            ------------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       704
 EXPRESSION (reg_addr == rom_ctrl_reg_pkg::ROM_CTRL_EXP_DIGEST_4_OFFSET)
            ------------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       705
 EXPRESSION (reg_addr == rom_ctrl_reg_pkg::ROM_CTRL_EXP_DIGEST_5_OFFSET)
            ------------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T10

 LINE       706
 EXPRESSION (reg_addr == rom_ctrl_reg_pkg::ROM_CTRL_EXP_DIGEST_6_OFFSET)
            ------------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T10

 LINE       707
 EXPRESSION (reg_addr == rom_ctrl_reg_pkg::ROM_CTRL_EXP_DIGEST_7_OFFSET)
            ------------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       710
 EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
             ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       710
 SUB-EXPRESSION (reg_re || reg_we)
                 ---1--    ---2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T7,T24
1	0	Covered	T1,T2,T3

 LINE       714
 EXPRESSION 
 Number  Term
      1  reg_we & 
      2  ((addr_hit[0] & ((|(4'b1 & (~reg_be))))) | (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | (addr_hit[2] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[3] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[4] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[5] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[6] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[7] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[8] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[9] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[10] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[11] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[12] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[13] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[14] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[15] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[16] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[17] & ((|(4'b1111 & (~reg_be)))))))

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T7,T24
1	1	Covered	T20,T21,T22

 LINE       714
 SUB-EXPRESSION 
 Number  Term
      1  (addr_hit[0] & ((|(4'b1 & (~reg_be))))) | 
      2  (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | 
      3  (addr_hit[2] & ((|(4'b1111 & (~reg_be))))) | 
      4  (addr_hit[3] & ((|(4'b1111 & (~reg_be))))) | 
      5  (addr_hit[4] & ((|(4'b1111 & (~reg_be))))) | 
      6  (addr_hit[5] & ((|(4'b1111 & (~reg_be))))) | 
      7  (addr_hit[6] & ((|(4'b1111 & (~reg_be))))) | 
      8  (addr_hit[7] & ((|(4'b1111 & (~reg_be))))) | 
      9  (addr_hit[8] & ((|(4'b1111 & (~reg_be))))) | 
     10  (addr_hit[9] & ((|(4'b1111 & (~reg_be))))) | 
     11  (addr_hit[10] & ((|(4'b1111 & (~reg_be))))) | 
     12  (addr_hit[11] & ((|(4'b1111 & (~reg_be))))) | 
     13  (addr_hit[12] & ((|(4'b1111 & (~reg_be))))) | 
     14  (addr_hit[13] & ((|(4'b1111 & (~reg_be))))) | 
     15  (addr_hit[14] & ((|(4'b1111 & (~reg_be))))) | 
     16  (addr_hit[15] & ((|(4'b1111 & (~reg_be))))) | 
     17  (addr_hit[16] & ((|(4'b1111 & (~reg_be))))) | 
     18  (addr_hit[17] & ((|(4'b1111 & (~reg_be))))))

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	-17-	-18-	Status	Tests
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	Covered	T2,T3,T4
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	Covered	T3,T4,T5
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	Covered	T3,T4,T10
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	Covered	T4,T16,T37
0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	0	Covered	T3,T4,T5
0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	0	0	Covered	T3,T4,T5
0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	Covered	T3,T4,T5
0	0	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	Covered	T3,T4,T5
0	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	Covered	T3,T4,T5
0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	Covered	T3,T4,T5
0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	Covered	T3,T4,T5
0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	Covered	T3,T5,T10
0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	0	Covered	T3,T4,T15
0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	Covered	T4,T5,T15
0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	Covered	T3,T4,T5
0	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	Covered	T3,T10,T15
0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	Covered	T3,T4,T5
0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	Covered	T1,T2,T5
1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	Covered	T5,T11,T70

 LINE       714
 SUB-EXPRESSION (addr_hit[0] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T11,T70

 LINE       714
 SUB-EXPRESSION (addr_hit[1] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Covered	T2,T5,T8
1	1	Covered	T1,T2,T5

 LINE       714
 SUB-EXPRESSION (addr_hit[2] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T10,T16
1	1	Covered	T3,T4,T5

 LINE       714
 SUB-EXPRESSION (addr_hit[3] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T16
1	1	Covered	T3,T10,T15

 LINE       714
 SUB-EXPRESSION (addr_hit[4] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5
1	1	Covered	T3,T4,T5

 LINE       714
 SUB-EXPRESSION (addr_hit[5] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T10,T16
1	1	Covered	T4,T5,T15

 LINE       714
 SUB-EXPRESSION (addr_hit[6] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T10,T37,T71
1	1	Covered	T3,T4,T15

 LINE       714
 SUB-EXPRESSION (addr_hit[7] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T15
1	1	Covered	T3,T5,T10

 LINE       714
 SUB-EXPRESSION (addr_hit[8] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T16
1	1	Covered	T3,T4,T5

 LINE       714
 SUB-EXPRESSION (addr_hit[9] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T10
1	1	Covered	T3,T4,T5

 LINE       714
 SUB-EXPRESSION (addr_hit[10] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T10,T15
1	1	Covered	T3,T4,T5

 LINE       714
 SUB-EXPRESSION (addr_hit[11] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T10,T16,T37
1	1	Covered	T3,T4,T5

 LINE       714
 SUB-EXPRESSION (addr_hit[12] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T10
1	1	Covered	T3,T4,T5

 LINE       714
 SUB-EXPRESSION (addr_hit[13] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T16
1	1	Covered	T3,T4,T5

 LINE       714
 SUB-EXPRESSION (addr_hit[14] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T10,T16
1	1	Covered	T3,T4,T5

 LINE       714
 SUB-EXPRESSION (addr_hit[15] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T10
1	1	Covered	T4,T16,T37

 LINE       714
 SUB-EXPRESSION (addr_hit[16] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T10,T16
1	1	Covered	T3,T4,T10

 LINE       714
 SUB-EXPRESSION (addr_hit[17] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T5,T10
1	1	Covered	T3,T4,T5

 LINE       736
 EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T72,T73,T74
1	0	1	Covered	T5,T6,T7
1	1	0	Covered	T20,T21,T22
1	1	1	Covered	T6,T7,T24

---

Branch Coverage for Module : rom_ctrl_regs_reg_top

	Line No.	Total	Covered	Percent
Branches		24	24	100.00
TERNARY	710	2	2	100.00
IF	68	3	3	100.00
CASE	766	19	19	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl_regs_reg_top.sv' or '../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl_regs_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	710	((reg_re || reg_we)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	68	if ((!rst_ni))
-2-:	70	if ((intg_err || reg_we_err))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T34,T35,T36
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	766	case (1'b1)

Branches:

-1-	Status	Tests
addr_hit[0]	Covered	T1,T2,T3
addr_hit[1]	Covered	T1,T2,T3
addr_hit[2]	Covered	T1,T2,T3
addr_hit[3]	Covered	T1,T2,T3
addr_hit[4]	Covered	T1,T2,T3
addr_hit[5]	Covered	T1,T2,T3
addr_hit[6]	Covered	T1,T2,T3
addr_hit[7]	Covered	T1,T2,T3
addr_hit[8]	Covered	T1,T2,T3
addr_hit[9]	Covered	T1,T2,T3
addr_hit[10]	Covered	T1,T2,T3
addr_hit[11]	Covered	T1,T2,T3
addr_hit[12]	Covered	T1,T2,T3
addr_hit[13]	Covered	T1,T2,T3
addr_hit[14]	Covered	T1,T2,T3
addr_hit[15]	Covered	T1,T2,T3
addr_hit[16]	Covered	T1,T2,T3
addr_hit[17]	Covered	T1,T2,T3
default	Covered	T1,T2,T3

---

Assert Coverage for Module : rom_ctrl_regs_reg_top

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
en2addrHit	653634982	176741	0	0
reAfterRv	653634982	176741	0	0
rePulse	653634982	50078	0	0
wePulse	653634982	126663	0	0

en2addrHit

Name	Attempts	Real Successes	Failures	Incomplete
Total	653634982	176741	0	0
T1	65862	1	0	0
T2	400170	35	0	0
T3	526803	32	0	0
T4	853562	32	0	0
T5	724565	29	0	0
T6	81441	2	0	0
T7	318871	9	0	0
T8	32978	1	0	0
T9	247527	0	0	0
T10	99446	32	0	0
T15	0	19	0	0

reAfterRv

Name	Attempts	Real Successes	Failures	Incomplete
Total	653634982	176741	0	0
T1	65862	1	0	0
T2	400170	35	0	0
T3	526803	32	0	0
T4	853562	32	0	0
T5	724565	29	0	0
T6	81441	2	0	0
T7	318871	9	0	0
T8	32978	1	0	0
T9	247527	0	0	0
T10	99446	32	0	0
T15	0	19	0	0

rePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	653634982	50078	0	0
T1	65862	1	0	0
T2	400170	35	0	0
T3	526803	32	0	0
T4	853562	32	0	0
T5	724565	29	0	0
T6	81441	0	0	0
T7	318871	0	0	0
T8	32978	1	0	0
T9	247527	0	0	0
T10	99446	32	0	0
T15	0	19	0	0
T16	0	64	0	0
T29	0	1	0	0

wePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	653634982	126663	0	0
T6	81441	2	0	0
T7	318871	9	0	0
T8	32978	0	0	0
T9	247527	0	0	0
T10	99446	0	0	0
T14	198344	0	0	0
T15	145268	0	0	0
T16	134344	0	0	0
T20	0	2207	0	0
T21	0	3468	0	0
T22	0	2741	0	0
T24	16615	19	0	0
T29	522405	0	0	0
T63	0	5	0	0
T75	0	6	0	0
T76	0	11	0	0
T77	0	13	0	0