Module Definition
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Module : rom_ctrl_regs_csr_assert_fpv
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rom_ctrl_csr_assert_0/rom_ctrl_regs_csr_assert_fpv.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.rom_ctrl_regs_csr_assert 100.00 100.00



Module Instance : tb.dut.rom_ctrl_regs_csr_assert

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.98 100.00 98.28 97.33 100.00 79.31 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Assert Coverage for Module : rom_ctrl_regs_csr_assert_fpv
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
TlulOOBAddrErr_A 459641450 4853461 0 0


TlulOOBAddrErr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 459641450 4853461 0 0
T10 186355 59172 0 0
T11 240559 0 0 0
T12 18626 0 0 0
T13 9335 0 0 0
T14 142288 0 0 0
T15 37355 0 0 0
T16 195877 0 0 0
T17 16592 0 0 0
T20 260367 0 0 0
T24 0 39584 0 0
T25 0 47338 0 0
T26 0 417608 0 0
T29 0 62976 0 0
T54 0 163921 0 0
T55 0 33269 0 0
T56 0 288672 0 0
T57 0 222797 0 0
T58 0 182085 0 0
T59 16573 0 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%