Unified Coverage Report :: Module :: rom_ctrl

Module : rom_ctrl

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.98	100.00	98.28	97.33		100.00	79.31

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	94.98	100.00	98.28	97.33		100.00	79.31

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.98	100.00	98.28	97.33		100.00	79.31

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.34	96.96	92.97	97.88	100.00	98.36	97.89

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_alert_tx[0].u_alert_sender	100.00			100.00
gen_fsm_scramble_enabled.u_checker_fsm	95.92	100.00	96.30	90.00	100.00	98.31	90.91
gen_rom_scramble_enabled.u_rom	97.06	88.24		100.00		100.00	100.00
regs_tlul_assert_device	100.00	100.00				100.00	100.00
rom_ctrl_regs_csr_assert	100.00						100.00
rom_tlul_assert_device	99.18	100.00				100.00	97.55
u_mux	95.24	100.00	85.71			100.00
u_reg_regs	99.72	99.41	99.21	100.00		100.00	100.00
u_tl_adapter_rom	94.13	91.45	84.93	99.07		95.18	100.00
u_tl_rom_h2d_buf	100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rom_ctrl

	Line No.	Total	Covered	Percent
TOTAL		65	65	100.00
CONT_ASSIGN	120	1	1	100.00
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	127	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	208	1	1	100.00
CONT_ASSIGN	254	1	1	100.00
CONT_ASSIGN	309	1	1	100.00
CONT_ASSIGN	410	1	1	100.00
CONT_ASSIGN	410	1	1	100.00
CONT_ASSIGN	410	1	1	100.00
CONT_ASSIGN	410	1	1	100.00
CONT_ASSIGN	410	1	1	100.00
CONT_ASSIGN	410	1	1	100.00
CONT_ASSIGN	410	1	1	100.00
CONT_ASSIGN	410	1	1	100.00
CONT_ASSIGN	411	1	1	100.00
CONT_ASSIGN	411	1	1	100.00
CONT_ASSIGN	411	1	1	100.00
CONT_ASSIGN	411	1	1	100.00
CONT_ASSIGN	411	1	1	100.00
CONT_ASSIGN	411	1	1	100.00
CONT_ASSIGN	411	1	1	100.00
CONT_ASSIGN	411	1	1	100.00
CONT_ASSIGN	413	1	1	100.00
CONT_ASSIGN	413	1	1	100.00
CONT_ASSIGN	413	1	1	100.00
CONT_ASSIGN	413	1	1	100.00
CONT_ASSIGN	413	1	1	100.00
CONT_ASSIGN	413	1	1	100.00
CONT_ASSIGN	413	1	1	100.00
CONT_ASSIGN	413	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	421	1	1	100.00
CONT_ASSIGN	423	1	1	100.00
CONT_ASSIGN	426	1	1	100.00
CONT_ASSIGN	427	1	1	100.00
CONT_ASSIGN	428	1	1	100.00
CONT_ASSIGN	429	1	1	100.00
CONT_ASSIGN	434	1	1	100.00
CONT_ASSIGN	438	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv' or '../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
120	1	1
125	1	1
126	1	1
127	1	1
128	1	1
131	1	1
208	1	1
254	1	1
309	1	1
410	8	8
411	8	8
413	8	8
414	8	8
416	8	8
417	8	8
421	1	1
423	1	1
426	1	1
427	1	1
428	1	1
429	1	1
434	1	1
438	1	1

---

Cond Coverage for Module : rom_ctrl

	Total	Covered	Percent
Conditions	58	57	98.28
Logical	58	57	98.28
Non-Logical	0	0
Event	0	0

 LINE       208
 EXPRESSION (rom_tl_i.a_valid ? rom_tl_i.a_address[2+:RomIndexWidth] : '0)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       254
 EXPRESSION (bus_rom_rvalid_raw & ((!internal_alert)))
             ---------1--------   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T15,T33
1	1	Covered	T1,T4,T5

 LINE       414
 EXPRESSION (exp_digest_de && (0 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       414
 SUB-EXPRESSION (0 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       414
 EXPRESSION (exp_digest_de && (1 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       414
 SUB-EXPRESSION (1 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       414
 EXPRESSION (exp_digest_de && (2 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       414
 SUB-EXPRESSION (2 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       414
 EXPRESSION (exp_digest_de && (3 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       414
 SUB-EXPRESSION (3 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       414
 EXPRESSION (exp_digest_de && (4 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       414
 SUB-EXPRESSION (4 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       414
 EXPRESSION (exp_digest_de && (5 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       414
 SUB-EXPRESSION (5 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       414
 EXPRESSION (exp_digest_de && (6 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       414
 SUB-EXPRESSION (6 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       414
 EXPRESSION (exp_digest_de && (7 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       414
 SUB-EXPRESSION (7 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       421
 EXPRESSION (rom_integrity_error | reg_integrity_error)
             ---------1---------   ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T36,T37
1	0	Not Covered

 LINE       423
 EXPRESSION (checker_alert | mux_alert)
             ------1------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T15,T33
1	0	Covered	T2,T3,T5

 LINE       434
 EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
             ---------1---------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T7,T9,T20
1	0	Covered	T1,T2,T3
1	1	Covered	T9,T20,T38

 LINE       438
 EXPRESSION (bus_integrity_error | checker_alert | mux_alert)
             ---------1---------   ------2------   ----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T5,T15,T33
0	1	0	Covered	T2,T3,T5
1	0	0	Covered	T3,T36,T37

---

Toggle Coverage for Module : rom_ctrl

	Total	Covered	Percent
Totals	61	56	91.80
Total Bits	2882	2805	97.33
Total Bits 0->1	1441	1402	97.29
Total Bits 1->0	1441	1403	97.36

Ports	61	56	91.80
Port Bits	2882	2805	97.33
Port Bits 0->1	1441	1402	97.29
Port Bits 1->0	1441	1403	97.36

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rom_cfg_i.cfg[3:0]	No	No		No		INPUT
rom_cfg_i.cfg_en	No	No		No		INPUT
rom_tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rom_tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T4,T6	Yes	T1,T2,T4	INPUT
rom_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
rom_tl_i.a_user.instr_type[3:0]	Yes	Yes	T2,T6,T15	Yes	T6,T15,T14	INPUT
rom_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
rom_tl_i.a_data[31:0]	Yes	Yes	T1,T4,T6	Yes	T1,T2,T4	INPUT
rom_tl_i.a_mask[3:0]	Yes	Yes	T1,T4,T6	Yes	T1,T4,T6	INPUT
rom_tl_i.a_address[31:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
rom_tl_i.a_source[7:0]	Yes	Yes	T1,T2,T4	Yes	T1,T4,T5	INPUT
rom_tl_i.a_size[1:0]	Yes	Yes	T1,T4,T6	Yes	T1,T2,T4	INPUT
rom_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
rom_tl_i.a_opcode[2:0]	Yes	Yes	T2,T6,T15	Yes	T6,T15,T20	INPUT
rom_tl_i.a_valid	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	INPUT
rom_tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
rom_tl_o.d_error	Yes	Yes	T17,T21,T22	Yes	T17,T21,T22	OUTPUT
rom_tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
rom_tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T4,*T5	Yes	T1,T4,T5	OUTPUT
rom_tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
rom_tl_o.d_data[31:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
rom_tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
rom_tl_o.d_source[7:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
rom_tl_o.d_size[1:0]	Yes	Yes	T1,T4,T6	Yes	T1,T4,T6	OUTPUT
rom_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
rom_tl_o.d_opcode[0]	Yes	Yes	*T17,*T21,*T22	Yes	T17,T21,T22	OUTPUT
rom_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
rom_tl_o.d_valid	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
regs_tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
regs_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
regs_tl_i.a_user.instr_type[3:0]	Yes	Yes	T3,T15,T38	Yes	T3,T15,T38	INPUT
regs_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_data[31:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
regs_tl_i.a_mask[3:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
regs_tl_i.a_address[31:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
regs_tl_i.a_source[7:0]	Yes	Yes	T1,T3,T5	Yes	T1,T3,T5	INPUT
regs_tl_i.a_size[1:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
regs_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_opcode[2:0]	Yes	Yes	T3,T9,T15	Yes	T3,T9,T15	INPUT
regs_tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
regs_tl_o.d_error	Yes	Yes	T17,T21,T22	Yes	T17,T21,T22	OUTPUT
regs_tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
regs_tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T3,*T4	Yes	T1,T3,T4	OUTPUT
regs_tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_data[31:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
regs_tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_source[7:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
regs_tl_o.d_size[1:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
regs_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
regs_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T2,T3,T5	Yes	T2,T3,T5	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T2,T3,T5	Yes	T2,T3,T5	OUTPUT
pwrmgr_data_o.good[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
pwrmgr_data_o.done[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T3,T4	OUTPUT
keymgr_data_o.valid	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	OUTPUT
keymgr_data_o.data[255:0]	Yes	Yes	T2,T4,T5	Yes	T1,T2,T4	OUTPUT
kmac_data_i.error	No	Yes	T2,T31,T32	No		INPUT
kmac_data_i.digest_share1[383:0]	Yes	Yes	T2,T5,T15	Yes	T5,T15,T11	INPUT
kmac_data_i.digest_share0[383:0]	Yes	Yes	T5,T15,T14	Yes	T1,T4,T5	INPUT
kmac_data_i.done	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
kmac_data_i.ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
kmac_data_o.last	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
kmac_data_o.strb[7:0]	No	No		No		OUTPUT
kmac_data_o.data[38:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
kmac_data_o.data[63:39]	No	No		No		OUTPUT
kmac_data_o.valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Module : rom_ctrl

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
TERNARY	208	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv' or '../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	208	(rom_tl_i.a_valid) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Module : rom_ctrl

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	29	29	100.00	23	79.31
Cover properties	0	0		0
Cover sequences	0	0		0
Total	29	29	100.00	23	79.31

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxOKnown_A	585975571	585618559	0	0
BusRomIndicesMatch_A	585952381	585606811	0	0
FpvSecCmFifoRptrCheck_A	585975571	0	0	0
FpvSecCmFifoWptrCheck_A	585975571	0	0	0
FpvSecCmRegWeOnehotCheck_A	585975571	140	0	0
KeymgrDataODataKnown_A	585975571	73942374	0	0
KeymgrDataODataKnown_AKnownEnable	585975571	585618559	0	0
KeymgrDataOValidKnown_A	585975571	585618559	0	0
KeymgrValidChk_A	585975571	0	0	624
KmacDataODataKnown_A	585975571	511423122	0	0
KmacDataODataKnown_AKnownEnable	585975571	585618559	0	0
KmacDataOValidKnown_A	585975571	585618559	0	0
PwrmgrDataChk_A	585975571	0	0	624
PwrmgrDataOKnown_A	585975571	585618559	0	0
RegsTlOAReadyKnown_A	585975571	585618559	0	0
RegsTlODDataKnown_A	585975571	10777931	0	0
RegsTlODDataKnown_AKnownEnable	585975571	585618559	0	0
RegsTlODValidKnown_A	585975571	585618559	0	0
RomTlOAReadyKnown_A	585975571	585618559	0	0
RomTlODDataKnown_A	585975571	17395419	0	0
RomTlODDataKnown_AKnownEnable	585975571	585618559	0	0
RomTlODValidKnown_A	585975571	585618559	0	0
StabilityChkKmac_A	585975571	511418253	0	0
StabilityChkkeymgr_A	585975571	73940123	0	0
TlAccessChk_A	585975571	511676185	0	0
gen_asserts_with_scrambling.FpvSecCmCheckerFsmAlert_A	585975571	140	0	0
gen_asserts_with_scrambling.FpvSecCmCompareAddrCtrCheck_A	585975571	0	0	0
gen_asserts_with_scrambling.FpvSecCmCompareFsmAlert_A	585975571	1092	0	0
gen_fsm_scramble_enabled_asserts.BusLocalEscChk_A	585975571	0	0	0

AlertTxOKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	585975571	585618559	0	0
T1	166851	166686	0	0
T2	490986	490819	0	0
T3	160680	158302	0	0
T4	563845	563560	0	0
T5	709499	709240	0	0
T6	132548	132439	0	0
T7	189740	189659	0	0
T8	269060	269002	0	0
T9	287720	287661	0	0
T10	17686	17619	0	0

BusRomIndicesMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	585952381	585606811	0	0
T1	166851	166686	0	0
T2	490986	490819	0	0
T3	160680	158302	0	0
T4	563845	563560	0	0
T5	709472	709229	0	0
T6	132548	132439	0	0
T7	189740	189659	0	0
T8	269060	269002	0	0
T9	287720	287661	0	0
T10	17686	17619	0	0

FpvSecCmFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	585975571	0	0	0

FpvSecCmFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	585975571	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	585975571	140	0	0
T3	160680	10	0	0
T4	563845	0	0	0
T5	709499	0	0	0
T6	132548	0	0	0
T7	189740	0	0	0
T8	269060	0	0	0
T9	287720	0	0	0
T10	17686	0	0	0
T13	696267	0	0	0
T15	329207	0	0	0
T36	0	10	0	0
T37	0	20	0	0
T39	0	20	0	0
T40	0	10	0	0
T41	0	10	0	0
T42	0	20	0	0
T43	0	10	0	0
T44	0	10	0	0
T45	0	20	0	0

KeymgrDataODataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	585975571	73942374	0	0
T1	166851	1742	0	0
T2	490986	61	0	0
T3	160680	34	0	0
T4	563845	2642	0	0
T5	709499	4084	0	0
T6	132548	1420	0	0
T7	189740	284	0	0
T8	269060	715	0	0
T9	287720	64	0	0
T10	17686	1222	0	0

KeymgrDataODataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	585975571	585618559	0	0
T1	166851	166686	0	0
T2	490986	490819	0	0
T3	160680	158302	0	0
T4	563845	563560	0	0
T5	709499	709240	0	0
T6	132548	132439	0	0
T7	189740	189659	0	0
T8	269060	269002	0	0
T9	287720	287661	0	0
T10	17686	17619	0	0

KeymgrDataOValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	585975571	585618559	0	0
T1	166851	166686	0	0
T2	490986	490819	0	0
T3	160680	158302	0	0
T4	563845	563560	0	0
T5	709499	709240	0	0
T6	132548	132439	0	0
T7	189740	189659	0	0
T8	269060	269002	0	0
T9	287720	287661	0	0
T10	17686	17619	0	0

KeymgrValidChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	585975571	0	0	624

KmacDataODataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	585975571	511423122	0	0
T1	166851	164875	0	0
T2	490986	490595	0	0
T3	160680	157042	0	0
T4	563845	560791	0	0
T5	709499	708667	0	0
T6	132548	130932	0	0
T7	189740	189297	0	0
T8	269060	268183	0	0
T9	287720	287563	0	0
T10	17686	16376	0	0

KmacDataODataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	585975571	585618559	0	0
T1	166851	166686	0	0
T2	490986	490819	0	0
T3	160680	158302	0	0
T4	563845	563560	0	0
T5	709499	709240	0	0
T6	132548	132439	0	0
T7	189740	189659	0	0
T8	269060	269002	0	0
T9	287720	287661	0	0
T10	17686	17619	0	0

KmacDataOValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	585975571	585618559	0	0
T1	166851	166686	0	0
T2	490986	490819	0	0
T3	160680	158302	0	0
T4	563845	563560	0	0
T5	709499	709240	0	0
T6	132548	132439	0	0
T7	189740	189659	0	0
T8	269060	269002	0	0
T9	287720	287661	0	0
T10	17686	17619	0	0

PwrmgrDataChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	585975571	0	0	624

PwrmgrDataOKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	585975571	585618559	0	0
T1	166851	166686	0	0
T2	490986	490819	0	0
T3	160680	158302	0	0
T4	563845	563560	0	0
T5	709499	709240	0	0
T6	132548	132439	0	0
T7	189740	189659	0	0
T8	269060	269002	0	0
T9	287720	287661	0	0
T10	17686	17619	0	0

RegsTlOAReadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	585975571	585618559	0	0
T1	166851	166686	0	0
T2	490986	490819	0	0
T3	160680	158302	0	0
T4	563845	563560	0	0
T5	709499	709240	0	0
T6	132548	132439	0	0
T7	189740	189659	0	0
T8	269060	269002	0	0
T9	287720	287661	0	0
T10	17686	17619	0	0

RegsTlODDataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	585975571	10777931	0	0
T1	166851	128	0	0
T2	490986	11	0	0
T3	160680	40	0	0
T4	563845	157	0	0
T5	709499	30	0	0
T6	132548	32	0	0
T7	189740	2	0	0
T8	269060	0	0	0
T9	287720	5	0	0
T10	17686	0	0	0
T13	0	32	0	0
T15	0	23	0	0

RegsTlODDataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	585975571	585618559	0	0
T1	166851	166686	0	0
T2	490986	490819	0	0
T3	160680	158302	0	0
T4	563845	563560	0	0
T5	709499	709240	0	0
T6	132548	132439	0	0
T7	189740	189659	0	0
T8	269060	269002	0	0
T9	287720	287661	0	0
T10	17686	17619	0	0

RegsTlODValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	585975571	585618559	0	0
T1	166851	166686	0	0
T2	490986	490819	0	0
T3	160680	158302	0	0
T4	563845	563560	0	0
T5	709499	709240	0	0
T6	132548	132439	0	0
T7	189740	189659	0	0
T8	269060	269002	0	0
T9	287720	287661	0	0
T10	17686	17619	0	0

RomTlOAReadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	585975571	585618559	0	0
T1	166851	166686	0	0
T2	490986	490819	0	0
T3	160680	158302	0	0
T4	563845	563560	0	0
T5	709499	709240	0	0
T6	132548	132439	0	0
T7	189740	189659	0	0
T8	269060	269002	0	0
T9	287720	287661	0	0
T10	17686	17619	0	0

RomTlODDataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	585975571	17395419	0	0
T1	166851	85	0	0
T2	490986	0	0	0
T3	160680	0	0	0
T4	563845	361	0	0
T5	709499	6	0	0
T6	132548	58	0	0
T7	189740	0	0	0
T8	269060	177	0	0
T9	287720	0	0	0
T10	17686	233	0	0
T11	0	601	0	0
T12	0	375	0	0
T13	0	65	0	0
T14	0	58	0	0

RomTlODDataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	585975571	585618559	0	0
T1	166851	166686	0	0
T2	490986	490819	0	0
T3	160680	158302	0	0
T4	563845	563560	0	0
T5	709499	709240	0	0
T6	132548	132439	0	0
T7	189740	189659	0	0
T8	269060	269002	0	0
T9	287720	287661	0	0
T10	17686	17619	0	0

RomTlODValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	585975571	585618559	0	0
T1	166851	166686	0	0
T2	490986	490819	0	0
T3	160680	158302	0	0
T4	563845	563560	0	0
T5	709499	709240	0	0
T6	132548	132439	0	0
T7	189740	189659	0	0
T8	269060	269002	0	0
T9	287720	287661	0	0
T10	17686	17619	0	0

StabilityChkKmac_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	585975571	511418253	0	0
T1	166851	164873	0	0
T2	490986	490593	0	0
T3	160680	157011	0	0
T4	563845	560787	0	0
T5	709499	708664	0	0
T6	132548	130930	0	0
T7	189740	189296	0	0
T8	269060	268182	0	0
T9	287720	287562	0	0
T10	17686	16375	0	0

StabilityChkkeymgr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	585975571	73940123	0	0
T1	166851	1740	0	0
T2	490986	60	0	0
T3	160680	28	0	0
T4	563845	2640	0	0
T5	709499	4072	0	0
T6	132548	1418	0	0
T7	189740	283	0	0
T8	269060	714	0	0
T9	287720	63	0	0
T10	17686	1221	0	0

TlAccessChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	585975571	511676185	0	0
T1	166851	164944	0	0
T2	490986	490758	0	0
T3	160680	158268	0	0
T4	563845	560918	0	0
T5	709499	708832	0	0
T6	132548	131019	0	0
T7	189740	189375	0	0
T8	269060	268287	0	0
T9	287720	287597	0	0
T10	17686	16397	0	0

gen_asserts_with_scrambling.FpvSecCmCheckerFsmAlert_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	585975571	140	0	0
T3	160680	10	0	0
T4	563845	0	0	0
T5	709499	0	0	0
T6	132548	0	0	0
T7	189740	0	0	0
T8	269060	0	0	0
T9	287720	0	0	0
T10	17686	0	0	0
T13	696267	0	0	0
T15	329207	0	0	0
T36	0	10	0	0
T37	0	20	0	0
T39	0	20	0	0
T40	0	10	0	0
T41	0	10	0	0
T42	0	20	0	0
T43	0	10	0	0
T44	0	10	0	0
T45	0	20	0	0

gen_asserts_with_scrambling.FpvSecCmCompareAddrCtrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	585975571	0	0	0

gen_asserts_with_scrambling.FpvSecCmCompareFsmAlert_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	585975571	1092	0	0
T3	160680	10	0	0
T4	563845	0	0	0
T5	709499	10	0	0
T6	132548	0	0	0
T7	189740	0	0	0
T8	269060	0	0	0
T9	287720	0	0	0
T10	17686	0	0	0
T13	696267	0	0	0
T15	329207	10	0	0
T28	0	5	0	0
T29	0	6	0	0
T33	0	10	0	0
T34	0	10	0	0
T35	0	5	0	0
T36	0	10	0	0
T46	0	5	0	0

gen_fsm_scramble_enabled_asserts.BusLocalEscChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	585975571	0	0	0