Module Definition
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Module : tlul_adapter_sram
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.22 96.92 83.05 88.89 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_tl_adapter_rom 92.22 96.92 83.05 88.89 100.00



Module Instance : tb.dut.u_tl_adapter_rom

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.22 96.92 83.05 88.89 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.13 91.45 84.93 99.07 95.18 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.98 100.00 98.28 97.33 100.00 79.31 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_cmd_intg_check.u_cmd_intg_chk 100.00 100.00 100.00 100.00
u_err 100.00 100.00 100.00 100.00 100.00
u_reqfifo 96.53 100.00 86.11 100.00 100.00
u_rsp_gen 100.00 100.00 100.00
u_rspfifo 95.02 100.00 85.11 90.00 100.00 100.00
u_sram_byte 100.00 100.00
u_sramreqfifo 92.36 100.00 75.00 94.44 100.00
u_tlul_data_integ_enc_data 0.00 0.00
u_tlul_data_integ_enc_instr 0.00 0.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : tlul_adapter_sram
Line No.TotalCoveredPercent
TOTAL656396.92
ALWAYS944375.00
CONT_ASSIGN10311100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN11511100.00
CONT_ASSIGN12011100.00
CONT_ASSIGN14011100.00
CONT_ASSIGN15211100.00
CONT_ASSIGN22411100.00
CONT_ASSIGN22511100.00
CONT_ASSIGN22611100.00
ALWAYS2318787.50
ALWAYS25166100.00
CONT_ASSIGN26511100.00
CONT_ASSIGN26911100.00
CONT_ASSIGN28811100.00
CONT_ASSIGN29311100.00
CONT_ASSIGN29911100.00
CONT_ASSIGN30311100.00
CONT_ASSIGN32311100.00
CONT_ASSIGN32411100.00
CONT_ASSIGN32511100.00
CONT_ASSIGN32611100.00
ALWAYS35666100.00
ALWAYS36855100.00
CONT_ASSIGN37911100.00
CONT_ASSIGN38011100.00
CONT_ASSIGN38911100.00
CONT_ASSIGN39011100.00
CONT_ASSIGN39211100.00
CONT_ASSIGN39311100.00
CONT_ASSIGN40011100.00
CONT_ASSIGN40311100.00
CONT_ASSIGN40711100.00
CONT_ASSIGN40811100.00
CONT_ASSIGN41011100.00
CONT_ASSIGN41711100.00
ALWAYS42333100.00
CONT_ASSIGN44411100.00
CONT_ASSIGN44911100.00
CONT_ASSIGN45400
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
94 1 1
95 1 1
96 1 1
97 0 1
MISSING_ELSE
103 1 1
108 1 1
115 1 1
120 1 1
140 1 1
152 1 1
224 1 1
225 1 1
226 1 1
231 1 1
233 1 1
234 1 1
236 1 1
237 1 1
238 1 1
241 0 1
244 1 1
251 1 1
253 1 1
254 1 1
255 1 1
257 1 1
260 1 1
265 1 1
269 1 1
288 1 1
293 1 1
299 1 1
303 1 1
323 1 1
324 1 1
325 1 1
326 1 1
356 1 1
357 1 1
359 1 1
360 1 1
361 1 1
362 1 1
MISSING_ELSE
368 1 1
369 1 1
371 1 1
372 1 1
373 1 1
MISSING_ELSE
379 1 1
380 1 1
389 1 1
390 1 1
392 1 1
393 1 1
400 1 1
403 1 1
407 1 1
408 1 1
410 1 1
417 1 1
423 1 1
427 1 1
429 1 1
MISSING_ELSE
444 1 1
449 1 1
454 unreachable


Cond Coverage for Module : tlul_adapter_sram
TotalCoveredPercent
Conditions1189883.05
Logical1189883.05
Non-Logical00
Event00

 LINE       96
 EXPRESSION (intg_error || rsp_fifo_error)
             -----1----    -------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10Not Covered

 LINE       103
 EXPRESSION (intg_error | rsp_fifo_error | intg_error_q)
             -----1----   -------2------   ------3-----
-1--2--3-StatusTests
000CoveredT1,T2,T3
001Not Covered
010Not Covered
100Not Covered

 LINE       108
 EXPRESSION 
 Number  Term
      1  ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData)) ? ((ByteAccess == 1'b0) ? ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2)) : 1'b0) : 1'b0)
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT2,T6,T15

 LINE       108
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------    ----------------2----------------
-1--2-StatusTests
00CoveredT1,T4,T5
01CoveredT2,T6,T15
10CoveredT2,T6,T15

 LINE       108
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T6,T15

 LINE       108
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T6,T15

 LINE       108
 SUB-EXPRESSION ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2))
                 ---------1---------    ----------2----------
-1--2-StatusTests
00CoveredT14,T16,T17
01CoveredT6,T14,T18
10CoveredT6,T15,T19

 LINE       108
 SUB-EXPRESSION (tl_i.a_mask != '1)
                ---------1---------
-1-StatusTests
0CoveredT6,T14,T18
1CoveredT2,T6,T15

 LINE       108
 SUB-EXPRESSION (tl_i.a_size != 2'h2)
                ----------1----------
-1-StatusTests
0CoveredT6,T15,T19
1CoveredT2,T6,T15

 LINE       120
 EXPRESSION (tl_i.a_opcode != Get)
            -----------1----------
-1-StatusTests
0CoveredT1,T3,T4
1CoveredT2,T6,T15

 LINE       140
 EXPRESSION (wr_attr_error | wr_vld_error | rd_vld_error | instr_error | tlul_error | intg_error)
             ------1------   ------2-----   ------3-----   -----4-----   -----5----   -----6----
-1--2--3--4--5--6-StatusTests
000000CoveredT1,T4,T5
000001Not Covered
000010CoveredT6,T15,T20
000100Not Covered
001000Unreachable
010000CoveredT17,T21,T22
100000Not Covered

 LINE       224
 EXPRESSION (tl_i_int.a_valid & tl_o_int.a_ready)
             --------1-------   --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T4,T6
11CoveredT1,T4,T5

 LINE       225
 EXPRESSION (tl_o_int.d_valid & tl_i_int.d_ready)
             --------1-------   --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T6,T11
11CoveredT1,T4,T5

 LINE       226
 EXPRESSION (req_o & gnt_i)
             --1--   --2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T4,T6
11CoveredT1,T4,T5

 LINE       237
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------
-1-StatusTests
0Not Covered
1CoveredT1,T4,T5

 LINE       254
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------
-1-StatusTests
0CoveredT17,T21,T22
1CoveredT1,T4,T5

 LINE       255
 EXPRESSION (rspfifo_rdata.error | reqfifo_rdata.error)
             ---------1---------   ---------2---------
-1--2-StatusTests
00CoveredT1,T4,T5
01CoveredT17,T21,T22
10Not Covered

 LINE       265
 EXPRESSION (d_valid & reqfifo_rvalid & rspfifo_rvalid & (reqfifo_rdata.op == OpRead))
             ---1---   -------2------   -------3------   --------------4-------------
-1--2--3--4-StatusTests
0111Not Covered
1011Not Covered
1101CoveredT17,T21,T22
1110CoveredT23,T24
1111CoveredT1,T4,T5

 LINE       265
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T5

 LINE       293
 EXPRESSION ((vld_rd_rsp & ((~d_error))) ? rspfifo_rdata.data : error_blanking_data)
             -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T5

 LINE       293
 SUB-EXPRESSION (vld_rd_rsp & ((~d_error)))
                 -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T4,T5

 LINE       299
 EXPRESSION ((vld_rd_rsp && reqfifo_rdata.error) ? error_blanking_integ : (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc))
             -----------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       299
 SUB-EXPRESSION (vld_rd_rsp && reqfifo_rdata.error)
                 -----1----    ---------2---------
-1--2-StatusTests
01CoveredT17,T21,T22
10CoveredT1,T4,T5
11Not Covered

 LINE       299
 SUB-EXPRESSION (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc)
                 -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T5

 LINE       303
 EXPRESSION ((d_valid && (reqfifo_rdata.op != OpRead)) ? AccessAck : AccessAckData)
             --------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT17,T21,T22

 LINE       303
 SUB-EXPRESSION (d_valid && (reqfifo_rdata.op != OpRead))
                 ---1---    --------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T4,T5
11CoveredT17,T21,T22

 LINE       303
 SUB-EXPRESSION (reqfifo_rdata.op != OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       303
 EXPRESSION (d_valid ? reqfifo_rdata.size : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T5

 LINE       303
 EXPRESSION (d_valid ? reqfifo_rdata.source : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T5

 LINE       303
 EXPRESSION (d_valid && d_error)
             ---1---    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T4,T5
11CoveredT17,T21,T22

 LINE       303
 EXPRESSION ((gnt_i | error_internal) & reqfifo_wready & sramreqfifo_wready)
             ------------1-----------   -------2------   ---------3--------
-1--2--3-StatusTests
011CoveredT1,T4,T6
101CoveredT4,T11,T12
110Not Covered
111CoveredT1,T2,T3

 LINE       303
 SUB-EXPRESSION (gnt_i | error_internal)
                 --1--   -------2------
-1--2-StatusTests
00CoveredT1,T4,T6
01CoveredT1,T2,T3
10CoveredT1,T4,T5

 LINE       323
 EXPRESSION (tl_i_int.a_valid & reqfifo_wready & ((~error_internal)))
             --------1-------   -------2------   ---------3---------
-1--2--3-StatusTests
011Not Covered
101CoveredT4,T11,T12
110CoveredT17,T21,T22
111CoveredT1,T4,T5

 LINE       325
 EXPRESSION (tl_i_int.a_valid & (tl_i_int.a_opcode inside {PutFullData, PutPartialData}))
             --------1-------   ----------------------------2---------------------------
-1--2-StatusTests
01CoveredT2,T6,T15
10CoveredT1,T4,T5
11CoveredT17,T21,T22

 LINE       326
 EXPRESSION (tl_i_int.a_valid ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T5

 LINE       362
 EXPRESSION ((tl_i_int.a_mask[i] && we_o) ? tl_i_int.a_data[(8 * i)+:8] : '0)
             --------------1-------------
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT17,T21,T22

 LINE       362
 SUB-EXPRESSION (tl_i_int.a_mask[i] && we_o)
                 ---------1--------    --2-
-1--2-StatusTests
01CoveredT17,T21,T22
10CoveredT1,T4,T5
11CoveredT17,T21,T22

 LINE       393
 EXPRESSION ((tl_i_int.a_opcode != Get) ? OpWrite : OpRead)
             -------------1------------
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT2,T6,T15

 LINE       393
 SUB-EXPRESSION (tl_i_int.a_opcode != Get)
                -------------1------------
-1-StatusTests
0CoveredT1,T3,T4
1CoveredT2,T6,T15

 LINE       407
 EXPRESSION (sram_ack & ((~we_o)))
             ----1---   ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T4,T5

 LINE       410
 EXPRESSION (rvalid_i & reqfifo_rvalid)
             ----1---   -------2------
-1--2-StatusTests
01CoveredT4,T11,T12
10Not Covered
11CoveredT1,T4,T5

 LINE       449
 EXPRESSION (((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error))) ? reqfifo_rready : 1'b0)
             ----------------------------1----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T5

 LINE       449
 SUB-EXPRESSION ((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error)))
                 --------------1-------------   ------------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT17,T21,T22
11CoveredT1,T4,T5

 LINE       449
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T5

Branch Coverage for Module : tlul_adapter_sram
Line No.TotalCoveredPercent
Branches 27 24 88.89
TERNARY 108 2 2 100.00
TERNARY 293 2 2 100.00
TERNARY 299 3 2 66.67
TERNARY 326 2 2 100.00
TERNARY 449 2 2 100.00
IF 94 3 2 66.67
IF 233 4 3 75.00
IF 253 3 3 100.00
IF 359 2 2 100.00
IF 371 2 2 100.00
IF 427 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 108 (((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))) ?

Branches:
-1-StatusTests
1 Covered T2,T6,T15
0 Covered T1,T4,T5


LineNo. Expression -1-: 293 ((vld_rd_rsp & (~d_error))) ?

Branches:
-1-StatusTests
1 Covered T1,T4,T5
0 Covered T1,T2,T3


LineNo. Expression -1-: 299 ((vld_rd_rsp && reqfifo_rdata.error)) ? -2-: 299 (vld_rd_rsp) ?

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Covered T1,T4,T5
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 326 (tl_i_int.a_valid) ?

Branches:
-1-StatusTests
1 Covered T1,T4,T5
0 Covered T1,T2,T3


LineNo. Expression -1-: 449 (((reqfifo_rdata.op == OpRead) & (~reqfifo_rdata.error))) ?

Branches:
-1-StatusTests
1 Covered T1,T4,T5
0 Covered T1,T2,T3


LineNo. Expression -1-: 94 if ((!rst_ni)) -2-: 96 if ((intg_error || rsp_fifo_error))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Not Covered
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 233 if (reqfifo_rvalid) -2-: 234 if (reqfifo_rdata.error) -3-: 237 if ((reqfifo_rdata.op == OpRead))

Branches:
-1--2--3-StatusTests
1 1 - Covered T17,T21,T22
1 0 1 Covered T1,T4,T5
1 0 0 Not Covered
0 - - Covered T1,T2,T3


LineNo. Expression -1-: 253 if (reqfifo_rvalid) -2-: 254 if ((reqfifo_rdata.op == OpRead))

Branches:
-1--2-StatusTests
1 1 Covered T1,T4,T5
1 0 Covered T17,T21,T22
0 - Covered T1,T2,T3


LineNo. Expression -1-: 359 if (tl_i_int.a_valid)

Branches:
-1-StatusTests
1 Covered T1,T4,T5
0 Covered T1,T2,T4


LineNo. Expression -1-: 371 if (tl_i_int.a_valid)

Branches:
-1-StatusTests
1 Covered T1,T4,T5
0 Covered T1,T2,T4


LineNo. Expression -1-: 427 if ((|sramreqfifo_rdata.mask))

Branches:
-1-StatusTests
1 Covered T1,T4,T5
0 Covered T1,T2,T3


Assert Coverage for Module : tlul_adapter_sram
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 14 14 100.00 14 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 14 14 100.00 14 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AddrOutKnown_A 585975571 585618559 0 0
DataIntgOptions_A 625 625 0 0
ReqOutKnown_A 585975571 585618559 0 0
SramDwHasByteGranularity_A 625 625 0 0
SramDwIsMultipleOfTlulWidth_A 625 625 0 0
TlOutKnown_A 585975571 585618559 0 0
TlOutPayloadKnown_A 585975571 17395419 0 0
TlOutPayloadKnown_AKnownEnable 585975571 585618559 0 0
WdataOutKnown_A 585975571 585618559 0 0
WeOutKnown_A 585975571 585618559 0 0
WmaskOutKnown_A 585975571 585618559 0 0
adapterNoReadOrWrite 625 625 0 0
rvalidHighReqFifoEmpty 585975571 65136 0 0
rvalidHighWhenRspFifoFull 585975571 65136 0 0


AddrOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 585975571 585618559 0 0
T1 166851 166686 0 0
T2 490986 490819 0 0
T3 160680 158302 0 0
T4 563845 563560 0 0
T5 709499 709240 0 0
T6 132548 132439 0 0
T7 189740 189659 0 0
T8 269060 269002 0 0
T9 287720 287661 0 0
T10 17686 17619 0 0

DataIntgOptions_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 625 625 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

ReqOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 585975571 585618559 0 0
T1 166851 166686 0 0
T2 490986 490819 0 0
T3 160680 158302 0 0
T4 563845 563560 0 0
T5 709499 709240 0 0
T6 132548 132439 0 0
T7 189740 189659 0 0
T8 269060 269002 0 0
T9 287720 287661 0 0
T10 17686 17619 0 0

SramDwHasByteGranularity_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 625 625 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

SramDwIsMultipleOfTlulWidth_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 625 625 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

TlOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 585975571 585618559 0 0
T1 166851 166686 0 0
T2 490986 490819 0 0
T3 160680 158302 0 0
T4 563845 563560 0 0
T5 709499 709240 0 0
T6 132548 132439 0 0
T7 189740 189659 0 0
T8 269060 269002 0 0
T9 287720 287661 0 0
T10 17686 17619 0 0

TlOutPayloadKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 585975571 17395419 0 0
T1 166851 85 0 0
T2 490986 0 0 0
T3 160680 0 0 0
T4 563845 361 0 0
T5 709499 6 0 0
T6 132548 58 0 0
T7 189740 0 0 0
T8 269060 177 0 0
T9 287720 0 0 0
T10 17686 233 0 0
T11 0 601 0 0
T12 0 375 0 0
T13 0 65 0 0
T14 0 58 0 0

TlOutPayloadKnown_AKnownEnable
NameAttemptsReal SuccessesFailuresIncomplete
Total 585975571 585618559 0 0
T1 166851 166686 0 0
T2 490986 490819 0 0
T3 160680 158302 0 0
T4 563845 563560 0 0
T5 709499 709240 0 0
T6 132548 132439 0 0
T7 189740 189659 0 0
T8 269060 269002 0 0
T9 287720 287661 0 0
T10 17686 17619 0 0

WdataOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 585975571 585618559 0 0
T1 166851 166686 0 0
T2 490986 490819 0 0
T3 160680 158302 0 0
T4 563845 563560 0 0
T5 709499 709240 0 0
T6 132548 132439 0 0
T7 189740 189659 0 0
T8 269060 269002 0 0
T9 287720 287661 0 0
T10 17686 17619 0 0

WeOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 585975571 585618559 0 0
T1 166851 166686 0 0
T2 490986 490819 0 0
T3 160680 158302 0 0
T4 563845 563560 0 0
T5 709499 709240 0 0
T6 132548 132439 0 0
T7 189740 189659 0 0
T8 269060 269002 0 0
T9 287720 287661 0 0
T10 17686 17619 0 0

WmaskOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 585975571 585618559 0 0
T1 166851 166686 0 0
T2 490986 490819 0 0
T3 160680 158302 0 0
T4 563845 563560 0 0
T5 709499 709240 0 0
T6 132548 132439 0 0
T7 189740 189659 0 0
T8 269060 269002 0 0
T9 287720 287661 0 0
T10 17686 17619 0 0

adapterNoReadOrWrite
NameAttemptsReal SuccessesFailuresIncomplete
Total 625 625 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

rvalidHighReqFifoEmpty
NameAttemptsReal SuccessesFailuresIncomplete
Total 585975571 65136 0 0
T1 166851 85 0 0
T2 490986 0 0 0
T3 160680 0 0 0
T4 563845 65 0 0
T5 709499 6 0 0
T6 132548 58 0 0
T7 189740 0 0 0
T8 269060 177 0 0
T9 287720 0 0 0
T10 17686 233 0 0
T11 0 100 0 0
T12 0 69 0 0
T13 0 65 0 0
T14 0 58 0 0

rvalidHighWhenRspFifoFull
NameAttemptsReal SuccessesFailuresIncomplete
Total 585975571 65136 0 0
T1 166851 85 0 0
T2 490986 0 0 0
T3 160680 0 0 0
T4 563845 65 0 0
T5 709499 6 0 0
T6 132548 58 0 0
T7 189740 0 0 0
T8 269060 177 0 0
T9 287720 0 0 0
T10 17686 233 0 0
T11 0 100 0 0
T12 0 69 0 0
T13 0 65 0 0
T14 0 58 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%