Unified Coverage Report :: Group :: tb.dut.u_rom_ctrl_cov_if::rom_ctrl_tlul_cg

Group : tb.dut.u_rom_ctrl_cov_if::rom_ctrl_tlul_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
87.50	87.50	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rom_ctrl_cov_0/rom_ctrl_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
rom_ctrl_tlul_cg	87.50	1	100	1	64	64

---

Group Instance : rom_ctrl_tlul_cg
Comment: TLUL interface behaviors

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
87.50	1	100	1	64	64

---

Summary for Group Instance rom_ctrl_tlul_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	1	7	87.50

Variables for Group Instance rom_ctrl_tlul_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regs_req_check	3	0	3	100.00	100	1	1	0
cp_rom_invalid_condition	2	1	1	50.00	100	1	1	0
cp_rom_req_check	3	0	3	100.00	100	1	1	0

Summary for Variable cp_regs_req_check

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_regs_req_check

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
req_after_done	2692201	1			T3	96		T5	4		T6	73806
req_and_done	7	1			T117	1		T118	1		T119	1
req_before_done	9	1			T49	1		T68	1		T85	1

---

Summary for Variable cp_rom_invalid_condition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	1	1	50.00

User Defined Bins for cp_rom_invalid_condition

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
check_invalid	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

check_valid

225158470

1

T1

196275

T2

81767

T3

537933

---

Summary for Variable cp_rom_req_check

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rom_req_check

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
req_after_done	3007388	1			T1	3		T3	189		T5	3
req_and_done	75	1			T1	1		T6	1		T11	1
req_before_done	292	1			T3	5		T6	2		T9	2