Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	74733	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1841496

1

T1

13

T3

19

T5

3

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	500619	1			T1	129		T3	206		T5	3
values[0x0]	694766	1			T6	11842		T14	92537		T15	36959
values[0x1]	720844	1			T6	12309		T14	96440		T15	38265

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	38959	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1877270

1

T1

80

T3

123

T5

3

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7058	1			T6	96		T63	16		T14	1003
valid_sources[0x01]	7639	1			T6	103		T14	983		T134	1
valid_sources[0x02]	7078	1			T6	117		T11	3		T14	932
valid_sources[0x03]	7797	1			T6	172		T14	974		T116	1
valid_sources[0x04]	7822	1			T6	104		T11	2		T14	968
valid_sources[0x05]	7651	1			T6	115		T45	2		T14	976
valid_sources[0x06]	7515	1			T6	127		T9	43		T11	2
valid_sources[0x07]	8617	1			T5	1		T6	111		T45	2
valid_sources[0x08]	7014	1			T6	142		T10	13		T11	2
valid_sources[0x09]	7958	1			T3	15		T6	115		T10	19
valid_sources[0x0a]	8686	1			T6	167		T11	1		T45	2
valid_sources[0x0b]	8576	1			T6	130		T14	989		T114	20
valid_sources[0x0c]	7399	1			T6	112		T14	1021		T76	1
valid_sources[0x0d]	7854	1			T6	117		T11	1		T14	1013
valid_sources[0x0e]	7097	1			T6	94		T11	1		T45	1
valid_sources[0x0f]	7256	1			T6	118		T11	3		T45	1
valid_sources[0x10]	7767	1			T6	136		T45	1		T14	997
valid_sources[0x11]	7522	1			T6	109		T45	1		T14	975
valid_sources[0x12]	7433	1			T6	131		T11	1		T45	2
valid_sources[0x13]	8381	1			T6	107		T13	47		T45	1
valid_sources[0x14]	7271	1			T6	182		T11	4		T14	943
valid_sources[0x15]	7210	1			T6	131		T75	7		T14	945
valid_sources[0x16]	6977	1			T3	1		T6	135		T14	979
valid_sources[0x17]	7661	1			T3	14		T6	113		T11	2
valid_sources[0x18]	7346	1			T6	128		T11	1		T12	1
valid_sources[0x19]	7069	1			T3	1		T6	136		T11	2
valid_sources[0x1a]	6992	1			T6	120		T14	928		T76	2
valid_sources[0x1b]	7532	1			T6	116		T11	2		T64	1
valid_sources[0x1c]	7269	1			T6	119		T45	2		T75	4
valid_sources[0x1d]	8170	1			T6	128		T11	1		T14	1014
valid_sources[0x1e]	7634	1			T6	135		T14	998		T76	2
valid_sources[0x1f]	7510	1			T6	127		T14	1011		T77	1
valid_sources[0x20]	7324	1			T6	95		T11	1		T45	2
valid_sources[0x21]	7476	1			T6	128		T45	1		T14	961
valid_sources[0x22]	7695	1			T6	133		T11	3		T14	972
valid_sources[0x23]	7462	1			T6	138		T14	959		T76	1
valid_sources[0x24]	8147	1			T6	121		T14	980		T76	1
valid_sources[0x25]	8962	1			T6	192		T63	23		T14	1014
valid_sources[0x26]	7089	1			T6	164		T45	2		T14	981
valid_sources[0x27]	7555	1			T6	156		T64	1		T14	948
valid_sources[0x28]	7438	1			T6	141		T9	21		T14	957
valid_sources[0x29]	8816	1			T6	139		T45	2		T14	951
valid_sources[0x2a]	7526	1			T6	125		T45	1		T14	997
valid_sources[0x2b]	7443	1			T3	2		T6	129		T11	1
valid_sources[0x2c]	8221	1			T6	149		T11	1		T45	1
valid_sources[0x2d]	7394	1			T6	111		T11	6		T14	994
valid_sources[0x2e]	6863	1			T3	2		T6	96		T11	1
valid_sources[0x2f]	7756	1			T6	156		T45	1		T14	1010
valid_sources[0x30]	7032	1			T6	146		T45	2		T14	1027
valid_sources[0x31]	7819	1			T6	173		T45	1		T14	967
valid_sources[0x32]	7406	1			T1	10		T3	10		T6	144
valid_sources[0x33]	8114	1			T6	123		T11	1		T14	936
valid_sources[0x34]	7707	1			T6	119		T11	2		T45	1
valid_sources[0x35]	7293	1			T6	148		T45	1		T14	986
valid_sources[0x36]	7787	1			T6	103		T11	2		T14	1001
valid_sources[0x37]	7236	1			T6	87		T11	2		T14	972
valid_sources[0x38]	7234	1			T6	96		T14	956		T76	1
valid_sources[0x39]	7759	1			T6	149		T11	2		T14	1001
valid_sources[0x3a]	7547	1			T6	145		T11	1		T14	1007
valid_sources[0x3b]	7322	1			T6	136		T11	2		T14	1022
valid_sources[0x3c]	8564	1			T6	116		T45	1		T14	1021
valid_sources[0x3d]	9859	1			T6	137		T64	2		T14	893
valid_sources[0x3e]	8004	1			T6	140		T14	1035		T77	1
valid_sources[0x3f]	7758	1			T6	165		T11	1		T14	981
valid_sources[0x40]	7286	1			T6	160		T14	932		T26	1
valid_sources[0x41]	7034	1			T6	149		T14	956		T115	8
valid_sources[0x42]	7238	1			T3	1		T6	138		T45	1
valid_sources[0x43]	7115	1			T6	158		T45	2		T14	942
valid_sources[0x44]	7229	1			T6	96		T14	1011		T116	3
valid_sources[0x45]	7156	1			T6	86		T11	2		T14	968
valid_sources[0x46]	7606	1			T6	124		T14	996		T77	2
valid_sources[0x47]	7073	1			T6	101		T11	1		T64	5
valid_sources[0x48]	8039	1			T6	140		T14	1076		T116	1
valid_sources[0x49]	8125	1			T6	135		T45	1		T14	970
valid_sources[0x4a]	7713	1			T6	147		T14	981		T116	1
valid_sources[0x4b]	7331	1			T6	134		T64	1		T14	1008
valid_sources[0x4c]	7332	1			T3	18		T6	121		T14	954
valid_sources[0x4d]	6928	1			T6	116		T45	1		T64	2
valid_sources[0x4e]	7309	1			T3	2		T6	113		T11	3
valid_sources[0x4f]	7234	1			T3	5		T6	149		T45	3
valid_sources[0x50]	7332	1			T6	89		T11	1		T14	929
valid_sources[0x51]	7229	1			T6	154		T11	8		T45	1
valid_sources[0x52]	8104	1			T6	104		T11	1		T14	1009
valid_sources[0x53]	8096	1			T6	182		T11	1		T14	1009
valid_sources[0x54]	7147	1			T6	158		T7	1		T45	2
valid_sources[0x55]	7174	1			T6	131		T11	1		T14	947
valid_sources[0x56]	7698	1			T3	5		T6	152		T11	1
valid_sources[0x57]	8098	1			T6	133		T14	1029		T116	1
valid_sources[0x58]	7877	1			T6	128		T11	1		T64	1
valid_sources[0x59]	7376	1			T3	10		T6	127		T11	3
valid_sources[0x5a]	7873	1			T6	124		T11	1		T14	935
valid_sources[0x5b]	7115	1			T6	155		T14	987		T76	1
valid_sources[0x5c]	7286	1			T6	124		T11	2		T14	966
valid_sources[0x5d]	7039	1			T6	133		T11	2		T64	1
valid_sources[0x5e]	7277	1			T3	3		T6	128		T75	2
valid_sources[0x5f]	7924	1			T3	5		T6	151		T45	1
valid_sources[0x60]	7314	1			T6	118		T14	1059		T76	1
valid_sources[0x61]	7553	1			T6	120		T11	1		T14	1002
valid_sources[0x62]	7570	1			T6	162		T11	1		T14	1000
valid_sources[0x63]	6926	1			T3	6		T6	117		T11	2
valid_sources[0x64]	7223	1			T6	144		T11	1		T14	991
valid_sources[0x65]	7466	1			T6	154		T11	1		T45	1
valid_sources[0x66]	7170	1			T6	132		T14	1043		T76	1
valid_sources[0x67]	7057	1			T6	91		T11	3		T64	1
valid_sources[0x68]	7727	1			T6	125		T63	15		T64	1
valid_sources[0x69]	7674	1			T6	129		T11	2		T14	1011
valid_sources[0x6a]	7657	1			T6	118		T11	1		T45	2
valid_sources[0x6b]	7379	1			T6	142		T64	1		T75	1
valid_sources[0x6c]	7231	1			T6	141		T11	4		T14	1032
valid_sources[0x6d]	7395	1			T6	141		T45	1		T14	983
valid_sources[0x6e]	8220	1			T6	140		T75	1		T14	971
valid_sources[0x6f]	7758	1			T5	1		T6	104		T14	919
valid_sources[0x70]	7664	1			T3	1		T6	162		T11	1
valid_sources[0x71]	7516	1			T6	147		T75	2		T14	979
valid_sources[0x72]	7071	1			T6	137		T11	1		T64	2
valid_sources[0x73]	7090	1			T6	97		T45	1		T14	1013
valid_sources[0x74]	7270	1			T6	152		T45	2		T14	1015
valid_sources[0x75]	7038	1			T6	109		T9	22		T11	1
valid_sources[0x76]	8434	1			T6	130		T64	1		T14	948
valid_sources[0x77]	7111	1			T1	15		T6	121		T11	1
valid_sources[0x78]	7903	1			T6	115		T11	1		T14	988
valid_sources[0x79]	7258	1			T6	91		T11	1		T45	2
valid_sources[0x7a]	7455	1			T6	134		T11	2		T14	978
valid_sources[0x7b]	7179	1			T6	163		T63	12		T14	932
valid_sources[0x7c]	7075	1			T6	81		T11	3		T14	969
valid_sources[0x7d]	7248	1			T3	1		T6	139		T14	988
valid_sources[0x7e]	7136	1			T6	82		T14	1104		T76	2
valid_sources[0x7f]	8283	1			T6	133		T11	2		T64	4
valid_sources[0x80]	7631	1			T6	149		T13	23		T14	968

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

463717

1

T1

13

T3

19

T5

3

values[0x0]

all_enables

biggest_size

688664

1

T6

11736

T14

91732

T15

36618

values[0x1]

all_enables

biggest_size

689115

1

T6

11741

T14

92241

T15

36465

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	139729	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1410260

1

T2

1

T3

51

T4

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	386668	1			T3	96		T5	15		T6	6867
values[0x0]	538726	1			T2	4		T4	6		T6	9690
values[0x1]	624595	1			T2	4		T4	5		T6	11110

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	62659	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1487330

1

T2

2

T3

60

T4

3

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7659	1			T3	2		T6	93		T45	1
valid_sources[0x01]	5410	1			T6	122		T12	3		T14	682
valid_sources[0x02]	5652	1			T6	102		T14	710		T24	1
valid_sources[0x03]	6031	1			T6	126		T14	629		T135	1
valid_sources[0x04]	6090	1			T6	106		T45	1		T14	832
valid_sources[0x05]	6205	1			T3	1		T6	81		T45	1
valid_sources[0x06]	6681	1			T6	116		T14	1251		T78	1
valid_sources[0x07]	6700	1			T6	111		T14	688		T43	1
valid_sources[0x08]	6018	1			T6	90		T45	1		T14	953
valid_sources[0x09]	6193	1			T6	113		T9	1		T14	815
valid_sources[0x0a]	5744	1			T6	97		T14	593		T136	1
valid_sources[0x0b]	7132	1			T6	100		T14	677		T137	1
valid_sources[0x0c]	5644	1			T6	116		T75	1		T14	902
valid_sources[0x0d]	5595	1			T6	102		T45	1		T14	640
valid_sources[0x0e]	5490	1			T6	92		T14	685		T138	1
valid_sources[0x0f]	5984	1			T6	76		T14	646		T78	1
valid_sources[0x10]	5452	1			T3	1		T6	105		T30	4
valid_sources[0x11]	5779	1			T6	91		T14	564		T20	1
valid_sources[0x12]	5433	1			T6	144		T14	686		T24	5
valid_sources[0x13]	6538	1			T6	118		T10	1		T14	810
valid_sources[0x14]	5648	1			T6	104		T14	689		T134	2
valid_sources[0x15]	6177	1			T6	134		T9	2		T14	784
valid_sources[0x16]	6459	1			T6	114		T45	2		T64	4
valid_sources[0x17]	6277	1			T3	1		T6	108		T14	970
valid_sources[0x18]	6172	1			T6	128		T10	2		T45	2
valid_sources[0x19]	6672	1			T6	78		T14	660		T78	2
valid_sources[0x1a]	6058	1			T6	105		T9	1		T14	960
valid_sources[0x1b]	6545	1			T3	6		T6	93		T12	4
valid_sources[0x1c]	6286	1			T3	2		T6	108		T14	688
valid_sources[0x1d]	5830	1			T6	102		T9	1		T14	1106
valid_sources[0x1e]	6187	1			T6	97		T45	1		T14	734
valid_sources[0x1f]	5542	1			T4	1		T6	105		T14	937
valid_sources[0x20]	6479	1			T6	116		T14	571		T78	3
valid_sources[0x21]	5732	1			T3	11		T6	84		T14	1027
valid_sources[0x22]	5811	1			T6	123		T30	2		T14	848
valid_sources[0x23]	5532	1			T6	93		T14	863		T81	2
valid_sources[0x24]	5915	1			T6	128		T14	777		T20	1
valid_sources[0x25]	6590	1			T6	112		T45	1		T14	999
valid_sources[0x26]	6587	1			T6	93		T12	6		T14	899
valid_sources[0x27]	5998	1			T6	121		T14	930		T138	1
valid_sources[0x28]	5754	1			T6	97		T14	814		T15	307
valid_sources[0x29]	6262	1			T6	100		T14	879		T136	2
valid_sources[0x2a]	5877	1			T6	110		T75	1		T14	969
valid_sources[0x2b]	6005	1			T3	1		T6	98		T45	1
valid_sources[0x2c]	5482	1			T6	94		T14	779		T43	1
valid_sources[0x2d]	5813	1			T6	114		T14	651		T139	2
valid_sources[0x2e]	5650	1			T6	107		T9	1		T14	817
valid_sources[0x2f]	5617	1			T3	2		T6	103		T45	1
valid_sources[0x30]	5730	1			T6	116		T9	1		T10	7
valid_sources[0x31]	5807	1			T6	104		T9	2		T14	623
valid_sources[0x32]	6291	1			T3	1		T6	107		T14	839
valid_sources[0x33]	6223	1			T6	96		T14	578		T20	1
valid_sources[0x34]	6587	1			T6	100		T14	551		T15	311
valid_sources[0x35]	6112	1			T6	100		T14	1146		T134	1
valid_sources[0x36]	6230	1			T6	109		T14	899		T136	1
valid_sources[0x37]	5717	1			T6	124		T9	1		T22	1
valid_sources[0x38]	6361	1			T6	113		T45	2		T14	619
valid_sources[0x39]	6663	1			T6	124		T14	553		T76	5
valid_sources[0x3a]	6263	1			T6	96		T14	955		T134	1
valid_sources[0x3b]	6154	1			T6	116		T14	918		T136	1
valid_sources[0x3c]	7494	1			T3	2		T6	104		T11	96
valid_sources[0x3d]	7411	1			T6	104		T10	1		T12	2
valid_sources[0x3e]	5540	1			T6	118		T14	636		T137	1
valid_sources[0x3f]	6437	1			T6	126		T9	1		T14	780
valid_sources[0x40]	5915	1			T6	136		T14	1017		T136	2
valid_sources[0x41]	5934	1			T6	147		T10	2		T14	1067
valid_sources[0x42]	5311	1			T6	105		T14	597		T134	1
valid_sources[0x43]	5476	1			T3	5		T6	100		T10	1
valid_sources[0x44]	6606	1			T6	113		T12	2		T14	834
valid_sources[0x45]	5880	1			T6	147		T14	681		T138	2
valid_sources[0x46]	5915	1			T6	123		T14	969		T59	1
valid_sources[0x47]	6834	1			T6	114		T75	2		T14	981
valid_sources[0x48]	6531	1			T6	103		T10	2		T45	1
valid_sources[0x49]	6169	1			T6	108		T9	3		T45	1
valid_sources[0x4a]	5667	1			T6	112		T45	2		T14	580
valid_sources[0x4b]	5603	1			T6	133		T45	2		T14	797
valid_sources[0x4c]	6762	1			T6	98		T14	779		T140	3
valid_sources[0x4d]	5884	1			T4	1		T6	111		T12	2
valid_sources[0x4e]	5969	1			T6	112		T10	10		T75	4
valid_sources[0x4f]	7593	1			T6	76		T14	751		T76	2
valid_sources[0x50]	6316	1			T6	118		T14	947		T24	3
valid_sources[0x51]	5457	1			T6	104		T14	1036		T141	1
valid_sources[0x52]	6184	1			T6	134		T14	959		T24	7
valid_sources[0x53]	6198	1			T6	103		T10	1		T14	738
valid_sources[0x54]	5339	1			T3	2		T6	105		T45	1
valid_sources[0x55]	5861	1			T6	116		T14	654		T20	1
valid_sources[0x56]	5882	1			T6	110		T12	3		T45	2
valid_sources[0x57]	5476	1			T6	118		T14	844		T15	348
valid_sources[0x58]	5325	1			T6	95		T14	887		T25	3
valid_sources[0x59]	6707	1			T6	103		T12	1		T45	1
valid_sources[0x5a]	6273	1			T6	95		T45	2		T75	2
valid_sources[0x5b]	5462	1			T6	71		T14	820		T141	1
valid_sources[0x5c]	5911	1			T6	109		T14	746		T136	1
valid_sources[0x5d]	6664	1			T6	115		T14	999		T78	1
valid_sources[0x5e]	5869	1			T3	5		T6	118		T14	593
valid_sources[0x5f]	6264	1			T6	99		T14	629		T15	356
valid_sources[0x60]	6730	1			T2	4		T6	124		T14	1137
valid_sources[0x61]	6930	1			T6	106		T14	763		T41	4
valid_sources[0x62]	5758	1			T6	104		T14	608		T134	2
valid_sources[0x63]	5988	1			T6	123		T14	709		T134	2
valid_sources[0x64]	6378	1			T6	103		T14	885		T24	2
valid_sources[0x65]	5890	1			T6	105		T75	1		T14	1040
valid_sources[0x66]	6190	1			T6	123		T14	560		T15	320
valid_sources[0x67]	5377	1			T6	96		T45	1		T14	624
valid_sources[0x68]	5850	1			T6	106		T14	1001		T137	1
valid_sources[0x69]	5518	1			T6	89		T14	992		T76	4
valid_sources[0x6a]	5482	1			T3	9		T6	80		T14	798
valid_sources[0x6b]	6288	1			T6	92		T14	859		T136	1
valid_sources[0x6c]	6288	1			T6	110		T14	833		T136	1
valid_sources[0x6d]	5918	1			T6	103		T14	961		T24	2
valid_sources[0x6e]	6039	1			T3	3		T6	135		T12	2
valid_sources[0x6f]	6343	1			T6	111		T14	780		T25	3
valid_sources[0x70]	6196	1			T6	111		T14	884		T139	8
valid_sources[0x71]	6384	1			T3	1		T6	114		T14	1053
valid_sources[0x72]	6733	1			T6	95		T14	757		T80	32
valid_sources[0x73]	5701	1			T6	121		T14	901		T15	337
valid_sources[0x74]	6364	1			T6	122		T14	894		T62	1
valid_sources[0x75]	6713	1			T6	111		T14	736		T59	1
valid_sources[0x76]	6518	1			T6	101		T12	1		T14	702
valid_sources[0x77]	6161	1			T6	95		T14	965		T138	2
valid_sources[0x78]	7213	1			T6	111		T14	864		T43	1
valid_sources[0x79]	6227	1			T6	91		T14	693		T136	1
valid_sources[0x7a]	5609	1			T6	97		T45	2		T14	793
valid_sources[0x7b]	6576	1			T6	103		T45	1		T14	1076
valid_sources[0x7c]	6338	1			T6	125		T14	866		T142	1
valid_sources[0x7d]	6430	1			T3	3		T6	108		T10	1
valid_sources[0x7e]	6214	1			T6	115		T14	683		T78	4
valid_sources[0x7f]	6222	1			T6	94		T14	945		T136	1
valid_sources[0x80]	6191	1			T4	1		T6	111		T75	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

356167

1

T3

51

T5

10

T6

6416

values[0x0]

all_enables

biggest_size

527482

1

T2

1

T4

1

T6

9513

values[0x1]

all_enables

biggest_size

526611

1

T6

9381

T14

69798

T59

1